超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理

A hardware implementation of a deep learning accelerator using SystemVerilog/Verilog, designed for efficient neural network inference. This project implements a systolic array-based matrix multiplication unit with various activation functions and supporting components.

Spring 2024 NYCU Integrated Circuit Design Laboratory (ICLAB)

Repository with SystemVerilog modules developed in the CADEMICS SV for design and verification course by SBMicro and Cadence Design Systems

FIR IP with AXI-Lite & AXI_stream

soc lab final project

SDRAM controller

A comprehensive development environment for Digital IC Design with Docker Compose!

Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host interface, and fused streaming datapath. Validated on chest X-ray pneumonia detection. Silicon Sprint 2026 — AUC.

bit-serial-Convolution-IP

A simplified 4X4 TPU

SHA-256 (Secure Hash Algorithm 256-bit) hardware is implemented in Verilog and C and verifcated in SystemVerilog.

This repository is all about design and verification...

Digital IC Design course assignments in Verilog RTL implementations

A digital IC design course implemented on FPGA in NYCU.

This repository contains all the designs done by Shreyas Singh in the VLSI related Labs-Digital VLSI design(5th semester) and Current Mode Analog VLSI desig(6th sem)

AES-128 (Advanced Encryption Standard 128-bit) module written in Verilog for FPGA/ASIC use.

System-oriented engineer with a background in Digital IC Design, currently mastering low-level programming at 42 Singapore.

Complete 64-bit 6T SRAM array with custom peripheral circuits in 120nm PDK. Achieved 3× FOM improvement through VDD/2 precharge and OTA-based sense amplifiers.