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Hey there 👋 I’m Shreyas, an ECE engineer passionate about blending hardware design, AI, and embedded systems to build the brains behind the bots.
Currently exploring:
🧩 RISC-V architectures for low-power SoC design
⚡ ASIC design flows (RTL ➜ Layout ➜ Tape-out simulation)
🤖 AI-based robotics and self-stabilizing drones
⚙️ Tech Stack
Domain Tools / Skills
💻 Languages C / C++ / Python / Verilog / MATLAB
🧠 AI & Simulation TensorFlow / Simulink / OpenCV
⚙️ VLSI Design Cadence Virtuoso / Synopsys ICC2 / Tanner L-Edit
🔩 Hardware Arduino Nano / ESP32 / MPU6050 / NRF24L01
🧬 Processor Design RISC-V ISA / Pipeline Simulation / RTL-to-GDSII Flow
🚀 Projects & Experiments
🛸 Self-Stabilizing Drone Controller — MPU6050 + PID-based flight logic
🧮 8-bit ALU & Multiplier (RTL Synthesis) — Built using Synopsys Design Compiler
💾 SRAM & FinFET Simulations — Post-layout analysis with Silvaco
🤖 AI-Driven Object Tracker — Vision-based robotic arm control
⚡ Tiny RISC-V Core — My journey into open hardware ❤️
📊 GitHub Stats
<p align="center"> <img src="https://github-readme-stats.vercel.app/api?username=ShreyasSingh&show_icons=true&theme=tokyonight" alt="GitHub Stats" /> <br> <img src="https://github-readme-streak-stats.herokuapp.com/?user=ShreyasSingh&theme=tokyonight" alt="GitHub Streak" /> <br> <img src="https://github-readme-activity-graph.vercel.app/graph?username=ShreyasSingh&theme=tokyo-night" alt="GitHub Activity Graph" /> </p>
🐍 Contribution Snake
<p align="center"> <img src="https://raw.githubusercontent.com/ShreyasSingh/ShreyasSingh/output/github-contribution-grid-snake.svg" alt="Snake animation" /> </p>
🎧 Now Playing on Spotify
<p align="center"> <img src="https://spotify-github-profile.vercel.app/api/view?uid=YOUR_SPOTIFY_ID&cover_image=true&theme=novatorem&show_offline=false&background_color=121212&interchange=true" alt="Spotify Now Playing" /> </p>
🧩 Fun Zone
“Between circuits and code lies consciousness.”
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💬 Random Fact: I once debugged an FPGA design at 3 AM listening to Don-Toliver No idea.
🎯 Goal: To design a neural-enabled RISC-V SoC for intelligent edge devices and have an ASIC tapeout by 2027.
🤖 Mood: "Make silicon think."
🔗 Connect with Me
<p align="center"> <a href="https://www.linkedin.com/in/YOUR-LINKEDIN-ID/"> <img src="https://img.shields.io/badge/LinkedIn-blue?logo=linkedin&logoColor=white" /> </a> <a href="mailto:yourmail@example.com"> <img src="https://img.shields.io/badge/Email-red?logo=gmail&logoColor=white" /> </a> <a href="https://github.com/ShreyasSingh"> <img src="https://img.shields.io/badge/GitHub-black?logo=github&logoColor=white" /> </a> </p>
<p align="center"> ⚡ *"From atoms to algorithms — I make both work together."* ⚡ </p> ```