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| 1 | +/* psoc6.c |
| 2 | + * |
| 3 | + * Copyright (C) 2020 wolfSSL Inc. |
| 4 | + * |
| 5 | + * This file is part of wolfBoot. |
| 6 | + * |
| 7 | + * wolfBoot is free software; you can redistribute it and/or modify |
| 8 | + * it under the terms of the GNU General Public License as published by |
| 9 | + * the Free Software Foundation; either version 2 of the License, or |
| 10 | + * (at your option) any later version. |
| 11 | + * |
| 12 | + * wolfBoot is distributed in the hope that it will be useful, |
| 13 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | + * GNU General Public License for more details. |
| 16 | + * |
| 17 | + * You should have received a copy of the GNU General Public License |
| 18 | + * along with this program; if not, write to the Free Software |
| 19 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA |
| 20 | + */ |
| 21 | + |
| 22 | +#include <stdint.h> |
| 23 | +#include <target.h> |
| 24 | +#include <string.h> |
| 25 | +#include "image.h" |
| 26 | + |
| 27 | +#include "cy_device_headers.h" |
| 28 | + |
| 29 | +#include "cy_flash.h" |
| 30 | +#include "cy_syspm.h" |
| 31 | +#include "cy_sysclk.h" |
| 32 | +#include "cy_syslib.h" |
| 33 | +#include "cy_ipc_drv.h" |
| 34 | + |
| 35 | +#include "psoc6_02_config.h" |
| 36 | + |
| 37 | +#define ROW_SIZE (0x1000) |
| 38 | +#define FLASH_BASE_ADDRESS (0x10000000) |
| 39 | +#define CPU_FREQ (100000000) |
| 40 | + |
| 41 | +uint8_t psoc6_write_buffer[ROW_SIZE]; |
| 42 | + |
| 43 | +#ifndef NVM_FLASH_WRITEONCE |
| 44 | +# error "wolfBoot psoc6 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE" |
| 45 | +#endif |
| 46 | + |
| 47 | +#ifdef __WOLFBOOT |
| 48 | +static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = |
| 49 | +{ |
| 50 | + .feedbackDiv = 100, |
| 51 | + .referenceDiv = 2, |
| 52 | + .outputDiv = 4, |
| 53 | + .lfMode = false, |
| 54 | + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, |
| 55 | +}; |
| 56 | + |
| 57 | +static void hal_set_pll(void) |
| 58 | +{ |
| 59 | + /*Set clock path 1 source to IMO, this feeds PLL1*/ |
| 60 | + Cy_SysClk_ClkPathSetSource(1U, CY_SYSCLK_CLKPATH_IN_IMO); |
| 61 | + |
| 62 | + /*Set the input for CLK_HF0 to the output of the PLL, which is on clock path 1*/ |
| 63 | + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); |
| 64 | + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); |
| 65 | + |
| 66 | + /*Set divider for CM4 clock to 0, might be able to lower this to save power if needed*/ |
| 67 | + Cy_SysClk_ClkFastSetDivider(0U); |
| 68 | + |
| 69 | + /*Set divider for peripheral and CM0 clock to 0 - This must be 0 to get fastest clock to CM0*/ |
| 70 | + Cy_SysClk_ClkPeriSetDivider(0U); |
| 71 | + |
| 72 | + /*Set divider for CM0 clock to 0*/ |
| 73 | + Cy_SysClk_ClkSlowSetDivider(0U); |
| 74 | + |
| 75 | + /*Set flash memory wait states */ |
| 76 | + Cy_SysLib_SetWaitStates(false, 100); |
| 77 | + |
| 78 | + /*Configure PLL for 100 MHz*/ |
| 79 | + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig)) |
| 80 | + { |
| 81 | + while(1) |
| 82 | + ; |
| 83 | + } |
| 84 | + /*Enable PLL*/ |
| 85 | + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u)) |
| 86 | + { |
| 87 | + while(1) |
| 88 | + ; |
| 89 | + } |
| 90 | +} |
| 91 | + |
| 92 | +void hal_init(void) |
| 93 | +{ |
| 94 | + Cy_PDL_Init(CY_DEVICE_CFG); |
| 95 | + Cy_Flash_Init(); |
| 96 | + hal_set_pll(); |
| 97 | +} |
| 98 | + |
| 99 | +void hal_prepare_boot(void) |
| 100 | +{ |
| 101 | +} |
| 102 | + |
| 103 | +#endif |
| 104 | + |
| 105 | + |
| 106 | +/* Only Row-aligned writes allowed. This is guaranteed by wolfBoot if NVM_CACHE is |
| 107 | + * in use (via NVM_FLASH_WRITEONCE=1), as unaligned writes become cached. |
| 108 | + */ |
| 109 | +int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) |
| 110 | +{ |
| 111 | + const uint8_t *src = data; |
| 112 | + if (len < ROW_SIZE) |
| 113 | + return -1; |
| 114 | + if ((((uint32_t)data) & FLASH_BASE_ADDRESS) == FLASH_BASE_ADDRESS) { |
| 115 | + if (len != ROW_SIZE) { |
| 116 | + return -1; |
| 117 | + } |
| 118 | + memcpy(psoc6_write_buffer, data, len); |
| 119 | + src = psoc6_write_buffer; |
| 120 | + } |
| 121 | + while (len) { |
| 122 | + Cy_Flash_ProgramRow(address, (const uint32_t *) src); |
| 123 | + len -= ROW_SIZE; |
| 124 | + if ((len > 0) && (len < ROW_SIZE)) |
| 125 | + return -1; |
| 126 | + } |
| 127 | + return 0; |
| 128 | +} |
| 129 | + |
| 130 | +void RAMFUNCTION hal_flash_unlock(void) |
| 131 | +{ |
| 132 | +} |
| 133 | + |
| 134 | +void RAMFUNCTION hal_flash_lock(void) |
| 135 | +{ |
| 136 | +} |
| 137 | + |
| 138 | +int RAMFUNCTION hal_flash_erase(uint32_t address, int len) |
| 139 | +{ |
| 140 | + int start = -1, end = -1; |
| 141 | + uint32_t end_address; |
| 142 | + uint32_t p = (uint32_t)address; |
| 143 | + if (len == 0) |
| 144 | + return -1; |
| 145 | + end_address = address + len; |
| 146 | + while ((end_address - p) >= ROW_SIZE) { |
| 147 | + Cy_Flash_EraseRow(p); |
| 148 | + p += ROW_SIZE; |
| 149 | + } |
| 150 | + return 0; |
| 151 | +} |
| 152 | + |
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