Skip to content

Commit 6a82cd5

Browse files
dgarskedgarske
authored
Merge pull request #47 from danielinux/nrf52_spi
nRF52 spi driver
2 parents fed4231 + 45055a4 commit 6a82cd5

6 files changed

Lines changed: 186 additions & 46 deletions

File tree

‎hal/nrf52.ld‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
MEMORY
22
{
3-
FLASH (rx) : ORIGIN = 0x0001f000, LENGTH = ##WOLFBOOT_PARTITION_BOOT_ADDRESS##
4-
RAM (rwx) : ORIGIN = 0x20002800, LENGTH = 0xD800
3+
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = ##WOLFBOOT_PARTITION_BOOT_ADDRESS##
4+
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
55
}
66

77
SECTIONS

‎hal/spi/spi_drv_nrf52.c‎

Lines changed: 123 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,123 @@
1+
/* spi_drv_nrf52.c
2+
*
3+
* Driver for the SPI back-end of the SPI_FLASH module.
4+
*
5+
* Example implementation for nrf52F4.
6+
*
7+
* Pinout: see spi_drv_nrf52.h
8+
*
9+
* Copyright (C) 2020 wolfSSL Inc.
10+
*
11+
* This file is part of wolfBoot.
12+
*
13+
* wolfBoot is free software; you can redistribute it and/or modify
14+
* it under the terms of the GNU General Public License as published by
15+
* the Free Software Foundation; either version 2 of the License, or
16+
* (at your option) any later version.
17+
*
18+
* wolfBoot is distributed in the hope that it will be useful,
19+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
20+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21+
* GNU General Public License for more details.
22+
*
23+
* You should have received a copy of the GNU General Public License
24+
* along with this program; if not, write to the Free Software
25+
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
26+
*/
27+
#include <stdint.h>
28+
#include "spi_drv.h"
29+
#include "spi_drv_nrf52.h"
30+
31+
#define SPI0 (0x40003000)
32+
#define SPI1 (0x40004000)
33+
#define SPI2 (0x40023000)
34+
35+
#define SPI SPI0
36+
#define SPI_TASKS_START *((volatile uint32_t *)(SPI + 0x10))
37+
#define SPI_TASKS_STOP *((volatile uint32_t *)(SPI + 0x14))
38+
#define SPI_EVENTS_ENDRX *((volatile uint32_t *)(SPI + 0x110))
39+
#define SPI_EVENTS_END *((volatile uint32_t *)(SPI + 0x118))
40+
#define SPI_EVENTS_ENDTX *((volatile uint32_t *)(SPI + 0x120))
41+
#define SPI_EV_RDY *((volatile uint32_t *)(SPI + 0x108))
42+
#define SPI_INTENSET *((volatile uint32_t *)(SPI + 0x304))
43+
#define SPI_INTENCLR *((volatile uint32_t *)(SPI + 0x308))
44+
#define SPI_ENABLE *((volatile uint32_t *)(SPI + 0x500))
45+
#define SPI_PSEL_SCK *((volatile uint32_t *)(SPI + 0x508))
46+
#define SPI_PSEL_MOSI *((volatile uint32_t *)(SPI + 0x50C))
47+
#define SPI_PSEL_MISO *((volatile uint32_t *)(SPI + 0x510))
48+
#define SPI_RXDATA *((volatile uint32_t *)(SPI + 0x518))
49+
#define SPI_TXDATA *((volatile uint32_t *)(SPI + 0x51C))
50+
#define SPI_FREQUENCY *((volatile uint32_t *)(SPI + 0x524))
51+
#define SPI_CONFIG *((volatile uint32_t *)(SPI + 0x554))
52+
53+
#define K125 0x02000000
54+
#define K250 0x04000000
55+
#define K500 0x08000000
56+
#define M1 0x10000000
57+
#define M2 0x20000000
58+
#define M4 0x40000000
59+
#define M8 0x80000000
60+
61+
void spi_cs_off(int pin)
62+
{
63+
GPIO_OUTSET = (1 << pin);
64+
while ((GPIO_OUT & (1 << pin)) == 0)
65+
;
66+
}
67+
68+
void spi_cs_on(int pin)
69+
{
70+
GPIO_OUTCLR = (1 << pin);
71+
while ((GPIO_OUT & (1 << pin)) != 0)
72+
;
73+
74+
}
75+
76+
uint8_t spi_read(void)
77+
{
78+
volatile uint32_t reg = SPI_EV_RDY;
79+
while (!reg)
80+
reg = SPI_EV_RDY;
81+
reg = SPI_RXDATA;
82+
SPI_EV_RDY = 0;
83+
return reg;
84+
}
85+
86+
void spi_write(const char byte)
87+
{
88+
uint32_t reg;
89+
SPI_EV_RDY = 0;
90+
SPI_TXDATA = (uint32_t)byte;
91+
reg = SPI_EV_RDY;
92+
while (!reg)
93+
reg = SPI_EV_RDY;
94+
}
95+
96+
97+
void spi_init(int polarity, int phase)
98+
{
99+
static int initialized = 0;
100+
if (!initialized) {
101+
initialized++;
102+
GPIO_PIN_CNF[SPI_CS_PIN] = GPIO_CNF_OUT;
103+
GPIO_PIN_CNF[SPI_SCLK_PIN] = GPIO_CNF_OUT;
104+
GPIO_PIN_CNF[SPI_MOSI_PIN] = GPIO_CNF_OUT;
105+
GPIO_PIN_CNF[SPI_MISO_PIN] = GPIO_CNF_IN;
106+
//GPIO_DIRSET = ((1 << SPI_CS_PIN) | (1 << SPI_SCLK_PIN) | (1 << SPI_MOSI_PIN));
107+
GPIO_OUTSET = (1 << SPI_CS_PIN);
108+
GPIO_OUTCLR = (1 << SPI_MOSI_PIN) | (1 << SPI_SCLK_PIN);
109+
110+
SPI_PSEL_MISO = SPI_MISO_PIN;
111+
SPI_PSEL_MOSI = SPI_MOSI_PIN;
112+
SPI_PSEL_SCK = SPI_SCLK_PIN;
113+
114+
SPI_FREQUENCY = M1;
115+
SPI_CONFIG = 0; /* mode 0,0 default */
116+
SPI_ENABLE = 1;
117+
}
118+
}
119+
120+
void spi_release(void)
121+
{
122+
123+
}

‎hal/spi/spi_drv_nrf52.h‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
/* spi_drv_nrf52.h
2+
*
3+
* wolfBoot is free software; you can redistribute it and/or modify
4+
* it under the terms of the GNU General Public License as published by
5+
* the Free Software Foundation; either version 2 of the License, or
6+
* (at your option) any later version.
7+
*
8+
* wolfBoot is distributed in the hope that it will be useful,
9+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
10+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11+
* GNU General Public License for more details.
12+
*
13+
* You should have received a copy of the GNU General Public License
14+
* along with this program; if not, write to the Free Software
15+
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
16+
*/
17+
18+
#ifndef SPI_DRV_NRF52_H_INCLUDED
19+
#define SPI_DRV_NRF52_H_INCLUDED
20+
#include <stdint.h>
21+
/** SPI settings **/
22+
23+
24+
#define GPIO_BASE (0x50000000)
25+
#define GPIO_OUT *((volatile uint32_t *)(GPIO_BASE + 0x504))
26+
#define GPIO_OUTSET *((volatile uint32_t *)(GPIO_BASE + 0x508))
27+
#define GPIO_OUTCLR *((volatile uint32_t *)(GPIO_BASE + 0x50C))
28+
#define GPIO_DIRSET *((volatile uint32_t *)(GPIO_BASE + 0x518))
29+
#define GPIO_PIN_CNF ((volatile uint32_t *)(GPIO_BASE + 0x700)) // Array
30+
31+
#define GPIO_CNF_IN 0
32+
#define GPIO_CNF_OUT 3
33+
34+
35+
/* Pinout (P0.x) */
36+
#if 1
37+
#define SPI_CS_PIN 13
38+
#define SPI_MOSI_PIN 4
39+
#define SPI_MISO_PIN 5
40+
#define SPI_SCLK_PIN 30
41+
#endif
42+
#if 0
43+
#define SPI_SCLK_PIN 5
44+
#define SPI_MISO_PIN 6
45+
#define SPI_MOSI_PIN 7
46+
#define SPI_CS_PIN 8
47+
#endif
48+
49+
50+
#define SPI_CS_FLASH SPI_CS_PIN
51+
52+
53+
54+
#endif

‎include/spi_drv.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,10 @@
3939
#include "hal/spi/spi_drv_zynq.h"
4040
#endif
4141

42+
#if defined(PLATFORM_nrf52)
43+
#include "hal/spi/spi_drv_nrf52.h"
44+
#endif
45+
4246
void spi_init(int polarity, int phase);
4347
void spi_write(const char byte);
4448
uint8_t spi_read(void);

test-app/app_nrf32.c renamed to test-app/app_nrf52.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ static void gpiotoggle(uint32_t pin)
4040

4141
void main(void)
4242
{
43-
uint32_t pin = 19;
43+
//uint32_t pin = 19;
44+
uint32_t pin = 6;
4445
int i;
4546
GPIO_PIN_CNF[pin] = 1; /* Output */
4647
while(1) {

‎test-app/app_stm32f4.c‎

Lines changed: 1 addition & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -290,47 +290,5 @@ void main(void) {
290290
while(1)
291291
;
292292
}
293-
#endif /** PLATFROM_stm32f4 **/
293+
#endif /** PLATFORM_stm32f4 **/
294294

295-
#ifdef PLATFORM_nrf52
296-
#define GPIO_BASE (0x50000000)
297-
#define GPIO_OUT *((volatile uint32_t *)(GPIO_BASE + 0x504))
298-
#define GPIO_OUTSET *((volatile uint32_t *)(GPIO_BASE + 0x508))
299-
#define GPIO_OUTCLR *((volatile uint32_t *)(GPIO_BASE + 0x50C))
300-
#define GPIO_PIN_CNF ((volatile uint32_t *)(GPIO_BASE + 0x700)) // Array
301-
302-
static void gpiotoggle(uint32_t pin)
303-
{
304-
uint32_t reg_val = GPIO_OUT;
305-
GPIO_OUTCLR = reg_val & (1 << pin);
306-
GPIO_OUTSET = (~reg_val) & (1 << pin);
307-
}
308-
309-
void main(void)
310-
{
311-
uint32_t pin = 19;
312-
int i;
313-
GPIO_PIN_CNF[pin] = 1; /* Output */
314-
while(1) {
315-
gpiotoggle(pin);
316-
for (i = 0; i < 800000; i++) // Wait a bit.
317-
asm volatile ("nop");
318-
}
319-
}
320-
321-
#endif
322-
323-
#ifdef PLATFORM_samr21
324-
void main(void) {
325-
asm volatile ("cpsie i");
326-
while(1)
327-
WFI();
328-
}
329-
#endif
330-
331-
#ifdef PLATFORM_hifive1
332-
void main(void) {
333-
while(1)
334-
;
335-
}
336-
#endif

0 commit comments

Comments
 (0)