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Fix Cortex-R5 ISR stack switching implementation
This implements missing ISR stack switching to prevent thread stack overflow. Comments described the logic but code was not implemented, causing ISRs to execute on thread stacks instead of dedicated system stack. Context Save (ISR Entry): - tx_thread_context_save.S: Add missing stack switch for IRQ - tx_thread_fiq_context_save.S: Add missing stack switch for FIQ - tx_thread_vectored_context_save.S: Add missing stack switch for vectored Context Restore (ISR Exit): - tx_thread_context_restore.S: Restore thread SP before popping registers (both __tx_thread_no_preempt_restore and __tx_thread_preempt_restore) - tx_thread_fiq_context_restore.S: Restore thread SP before popping registers (both FIQ no-preempt and preempt paths) Implementation: ISR Entry (Save): STMDB sp!, {r2, r10, r12, lr} @ Save registers on thread stack LDR r1, =_tx_thread_system_stack_ptr @ Get system stack address STR sp, [r0, eclipse-threadx#8] @ Save thread SP to TCB LDR sp, [r1] @ Switch to system stack ISR Exit (Restore): LDR sp, [r0, eclipse-threadx#8] @ Restore thread SP from TCB LDMIA sp!, {r0, r10, r12, lr} @ Pop from thread stack Rationale: - Prevents stack overflow: ISRs execute on dedicated system stack - Preserves thread stack integrity for debugging and stack checking - Matches design intent documented in inline comments - Required for nested interrupt support and stack overflow detection - Critical for lockstep mode (deterministic stack usage) Execution Flow: 1. IRQ/FIQ occurs while thread running 2. Save minimal context to thread stack 3. Save thread SP to TCB at offset eclipse-threadx#8 (tx_thread_stack_ptr field) 4. Switch SP to system stack 5. ISR executes on system stack 6. Restore thread SP from TCB before returning 7. Pop saved context from thread stack 8. Return to interrupted thread All Paths Fixed: - IRQ no-preempt restore: Thread continues without context switch - IRQ preempt restore: Higher-priority thread needs to run - FIQ no-preempt restore: FIQ returns to same thread - FIQ preempt restore: FIQ triggers thread switch - Vectored interrupts: Return through context_restore (already fixed) Impact: - Fixes stack overflow risk from nested/heavy ISRs - Enables TX_ENABLE_STACK_CHECKING to work correctly - Debugging tools can now properly inspect thread stacks - System stack usage isolated from thread stack usage
1 parent 41840f0 commit 162e286

5 files changed

Lines changed: 25 additions & 7 deletions

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‎ports/cortex_r5/gnu/src/tx_thread_context_restore.S‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -158,6 +158,8 @@ __tx_thread_no_preempt_restore:
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@
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@ /* Pickup the saved stack pointer. */
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@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr;
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@
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LDR sp, [r0, #8] @ Restore thread stack pointer
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@
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@ /* Recover the saved context and return to the point of interrupt. */
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@
@@ -171,6 +173,7 @@ __tx_thread_no_preempt_restore:
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@ {
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__tx_thread_preempt_restore:
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@
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LDR sp, [r0, #8] @ Restore thread stack pointer
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LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers
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MOV r1, lr @ Save lr (point of interrupt)
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MOV r2, #SVC_MODE @ Build SVC mode CPSR

‎ports/cortex_r5/gnu/src/tx_thread_context_save.S‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -140,16 +140,20 @@ __tx_thread_not_nested_save:
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@ /* Save minimal context of interrupted thread. */
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@
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MRS r2, SPSR @ Pickup saved SPSR
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SUB lr, lr, #4 @ Adjust point of interrupt
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SUB lr, lr, #4 @ Adjust point of interrupt
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STMDB sp!, {r2, r10, r12, lr} @ Store other registers
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@
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@ /* Save the current stack pointer in the thread's control block. */
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@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
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@
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LDR r1, =_tx_thread_system_stack_ptr @ Pickup system stack pointer address
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STR sp, [r0, #8] @ Save thread stack pointer
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@
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@ /* Switch to the system stack. */
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@ sp = _tx_thread_system_stack_ptr@
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@
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MOV r10, #0 @ Clear stack limit
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LDR sp, [r1] @ Switch to system stack
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MOV r10, #0 @ Clear stack limit
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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@

‎ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -160,6 +160,8 @@ __tx_thread_fiq_no_preempt_restore:
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@
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@ /* Pickup the saved stack pointer. */
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@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr;
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@
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LDR sp, [r0, #8] @ Restore thread stack pointer
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@
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@ /* Recover the saved context and return to the point of interrupt. */
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@
@@ -173,6 +175,7 @@ __tx_thread_fiq_no_preempt_restore:
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@ {
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__tx_thread_fiq_preempt_restore:
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@
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LDR sp, [r0, #8] @ Restore thread stack pointer
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LDMIA sp!, {r3, lr} @ Recover temporarily saved registers
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MOV r1, lr @ Save lr (point of interrupt)
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MOV r2, #SVC_MODE @ Build SVC mode CPSR

‎ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -137,19 +137,23 @@ __tx_thread_fiq_not_nested_save:
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@ /* Save minimal context of interrupted thread. */
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@
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MRS r2, SPSR @ Pickup saved SPSR
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SUB lr, lr, #4 @ Adjust point of interrupt
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SUB lr, lr, #4 @ Adjust point of interrupt
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STMDB sp!, {r2, lr} @ Store other registers, Note that we don't
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@ @ need to save sl and ip since FIQ has
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@ @ copies of these registers. Nested
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@ @ need to save sl and ip since FIQ has
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@ @ copies of these registers. Nested
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@ @ interrupt processing does need to save
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@ @ these registers.
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@
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@ /* Save the current stack pointer in the thread's control block. */
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@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
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@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
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@
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LDR r1, =_tx_thread_system_stack_ptr @ Pickup system stack pointer address
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STR sp, [r0, #8] @ Save thread stack pointer
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@
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@ /* Switch to the system stack. */
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@ sp = _tx_thread_system_stack_ptr;
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@ sp = _tx_thread_system_stack_ptr;
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@
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LDR sp, [r1] @ Switch to system stack
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MOV r10, #0 @ Clear stack limit
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY

‎ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,10 +135,14 @@ __tx_thread_not_nested_save:
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@
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@ /* Save the current stack pointer in the thread's control block. */
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@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
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@
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LDR r1, =_tx_thread_system_stack_ptr @ Pickup system stack pointer address
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STR sp, [r0, #8] @ Save thread stack pointer
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@
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@ /* Switch to the system stack. */
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@ sp = _tx_thread_system_stack_ptr;
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@
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LDR sp, [r1] @ Switch to system stack
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MOV r10, #0 @ Clear stack limit
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY

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