Fix Cortex-R5 memory barrier for interrupt control

This adds missing memory barriers to interrupt disable/restore ops to
prevent compiler reordering and ensure proper memory ordering on
ARMv7-R.
- tx_port.h: Add DMB/ISB barriers and "memory"/"cc" clobbers to
  TX_DISABLE and TX_RESTORE inline assembly macros
- tx_thread_interrupt_disable.S: Add DMB/ISB after CPSID instruction
- tx_thread_interrupt_restore.S: Add DMB before MSR, ISB after

Implementation:
- TX_DISABLE: MRS → CPSID → DMB → ISB (acquire semantics)
- TX_RESTORE: DMB → MSR → ISB (release semantics)
- Uses DMB (Data Memory Barrier) for optimal lockstep performance
- ISB ensures pipeline synchronization for deterministic interrupt timing

Rationale:
- "memory" clobber prevents compiler from reordering memory operations
- "cc" clobber indicates CPSR condition codes are modified
- DMB ensures memory ordering without waiting for completion (vs DSB)
- ISB flushes pipeline to ensure CPSID/MSR takes effect immediately
- DMB before MSR in restore ensures stores are visible before interrupts
  re-enable (release semantics)

Impact:
- Fixes race conditions in queue/mutex operations under -O3 optimization
- Prevents data corruption from out-of-order memory access
- Lockstep-safe: identical execution on both cores in dual-core R5F

Reference: ARMv7-R Architecture Manual (DDI 0406C), Sections B1.8.14, A3.8.3
Fixes: eclipse-threadx#334

Author: jserv

ports/cortex_r5/gnu/inc/tx_port.h

@@ -287,12 +287,12 @@ unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
 #define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
 
 #ifdef TX_ENABLE_FIQ_SUPPORT
-#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) : : "memory", "cc");
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR \n CPSID if \n DMB \n ISB ": "=r" (interrupt_save) : : "memory", "cc");
 #else
-#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) : : "memory", "cc");
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR \n CPSID i \n DMB \n ISB ": "=r" (interrupt_save) : : "memory", "cc");
 #endif
 
-#define TX_RESTORE                              asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) );
+#define TX_RESTORE                              asm volatile (" DMB \n MSR CPSR_c,%0 \n ISB "::"r" (interrupt_save) : "memory", "cc");
 
 #endif
 

ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S

@@ -93,8 +93,10 @@ _tx_thread_interrupt_disable:
 #ifdef TX_ENABLE_FIQ_SUPPORT
     CPSID   if                                  @ Disable IRQ and FIQ
 #else
-    CPSID   i                                   @ Disable IRQ 
+    CPSID   i                                   @ Disable IRQ
 #endif
+    DMB                                         @ Memory barrier (acquire semantics)
+    ISB                                         @ Flush pipeline
 
 #ifdef __THUMB_INTERWORK
     BX      lr                                  @ Return to caller

ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S

@@ -87,7 +87,9 @@ _tx_thread_interrupt_restore:
 @
 @    /* Apply the new interrupt posture.  */
 @
+    DMB                                         @ Memory barrier (release semantics)
     MSR     CPSR_c, r0                          @ Setup new CPSR
+    ISB                                         @ Synchronize context
 #ifdef __THUMB_INTERWORK
     BX      lr                                  @ Return to caller
 #else