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    92 repositories

    • core-cc

      Public
      A comprehensive framework for analyzing, and comparing different Error Correction Code (ECC) implementations with support for hardware verification, detailed pe…
      Verilog
      •
      Other
      •1•1•0•0•Updated Mar 4, 2026Mar 4, 2026

    • core-ddr2

      Public
      This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and map…
      memoryrtlverilog
      memoryrtlverilogdigital-designmemory-controllerddr2
      Verilog
      •
      Creative Commons Attribution 4.0 International
      •1•1•0•0•Updated Feb 15, 2026Feb 15, 2026

    • digital_verification_news

      Public
      Daily Papers is an automated literature aggregation pipeline that collects, normalizes, and publishes up-to-date research digests for configurable topics. It qu…
      Python
      •
      Other
      •0•2•0•0•Updated Feb 13, 2026Feb 13, 2026

    • .github

      Public
      1•1•0•0•Updated Feb 7, 2026Feb 7, 2026

    • verification_planning_management

      Public
      A self-paced course for learning verification planning and management using SystemVerilog/UVM. This repository provides a complete learning path from initial ve…
      Shell
      •
      Other
      •2•4•0•0•Updated Feb 7, 2026Feb 7, 2026

    • learn_uart_spi_i2c

      Public
      A progressive course in digital design and verification covering UART, SPI, and I²C — from specification and RTL through UVM-based verification with Verilator. …
      SystemVerilog
      •
      Other
      •1•11•0•0•Updated Feb 7, 2026Feb 7, 2026

    • learn_verilog_systemverilog

      Public
      A version-centric learning path for Verilog and SystemVerilog from IEEE 1364-1995 through IEEE 1800-2017. This project provides modules, examples, DUTs, tests, …
      SystemVerilog
      •
      Other
      •1•5•0•0•Updated Feb 3, 2026Feb 3, 2026

    • learn_unix_git

      Public
      Unix, Git, and tooling basics for students taking digital design and verification courses.
      Shell
      •
      Other
      •0•9•0•0•Updated Feb 2, 2026Feb 2, 2026

    • core

      Public
      This repository contains a comprehensive collection of parameterized and configurable RTL modules written in Verilog, organized by category for EDA research and…
      C++
      •
      Other
      •3•3•0•0•Updated Jan 25, 2026Jan 25, 2026

    • learn_digital_verilog

      Public
      This comprehensive course teaches you how to design digital circuits using Verilog and SystemVerilog. Starting with digital logic fundamentals and tool setup, y…
      Verilog
      •0•7•0•0•Updated Jan 25, 2026Jan 25, 2026

    • learn_verilator_iverilog

      Public
      This comprehensive course teaches you how to write effective testbenches for RTL verification using Verilog, SystemVerilog, iverilog, and Verilator. The course …
      Verilog
      •3•7•0•0•Updated Jan 25, 2026Jan 25, 2026

    • learn_uvm2017_sv_verilator

      Public
      A comprehensive, modular learning path for mastering UVM (Universal Verification Methodology) using SystemVerilog (IEEE 1800.2-2017) with progressive complexity…
      C++
      •3•13•0•0•Updated Jan 25, 2026Jan 25, 2026

    • learn_uvm_pyuvm

      Public
      A comprehensive, modular learning path for mastering UVM (Universal Verification Methodology) and pyuvm (Python UVM implementation) with progressive complexity …
      C++
      •
      Other
      •2•31•0•0•Updated Jan 25, 2026Jan 25, 2026

    • pyvsc

      Public
      Python packages providing a library for Verification Stimulus and Coverage
      Python
      •
      Apache License 2.0
      •32•4•0•0•Updated Jan 15, 2026Jan 15, 2026

    • repo_analysis

      Public
      This repository serves as an index and documentation hub for repositories maintained by the Universal Verification Methodology Community on GitHub. The organiza…
      0•5•0•0•Updated Jan 15, 2026Jan 15, 2026

    • pyEDAA.UCIS

      Public
      Unified Coverage Interoperability Standard (UCIS)
      Python
      •
      Other
      •1•3•0•0•Updated Jan 12, 2026Jan 12, 2026

    • uvm-python

      Public
      UVM 1.2 port to Python
      Python
      •
      Apache License 2.0
      •48•4•0•0•Updated Jan 11, 2026Jan 11, 2026

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      •
      Other
      •313•3•0•0•Updated Jan 11, 2026Jan 11, 2026

    • cocotb

      Public
      cocotb: Python-based chip (RTL) verification
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •635•3•0•0•Updated Jan 11, 2026Jan 11, 2026

    • rggen

      Public
      Code generation tool for control and status registers
      Ruby
      •
      MIT License
      •57•3•0•0•Updated Jan 7, 2026Jan 7, 2026

    • pyuvm

      Public
      The UVM written in Python
      Python
      •
      Other
      •101•4•0•0•Updated Dec 26, 2025Dec 26, 2025

    • hwt

      Public
      VHDL/Verilog/SystemC code generator, simulator API written in python/c++
      Python
      •
      MIT License
      •30•3•0•0•Updated Dec 23, 2025Dec 23, 2025

    • system_verilog_enviroment_ALU_example

      Public
      This repo. explains how to build a SystemVerilog environment for verifying an ALU design.
      SystemVerilog
      •1•4•0•0•Updated Dec 20, 2025Dec 20, 2025

    • PeakRDL

      Public
      Control and status register code generator toolchain
      Python
      •
      GNU Lesser General Public License v3.0
      •40•3•0•0•Updated Dec 3, 2025Dec 3, 2025

    • verilator-uvm-example

      Public
      Example of how to use UVM with Verilator
      SystemVerilog
      •
      Apache License 2.0
      •8•3•0•0•Updated Dec 1, 2025Dec 1, 2025

    • PeakRDL-uvm

      Public
      Generate UVM register model from compiled SystemRDL input
      Python
      •
      GNU Lesser General Public License v3.0
      •35•3•0•0•Updated Nov 25, 2025Nov 25, 2025

    • uvm-verilator

      Public
      SystemVerilog
      •
      Apache License 2.0
      •30•3•0•0•Updated Nov 11, 2025Nov 11, 2025

    • pyucis

      Public
      Python API to Unified Coverage Interoperability Standard (UCIS) Data
      Python
      •
      Apache License 2.0
      •14•3•0•0•Updated Oct 21, 2025Oct 21, 2025

    • yuu_ahb

      Public
      UVM AHB VIP
      SystemVerilog
      •
      MIT License
      •24•4•0•0•Updated Sep 13, 2025Sep 13, 2025

    • Surelog

      Public
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Window…
      C++
      •
      Apache License 2.0
      •79•3•0•0•Updated Sep 6, 2025Sep 6, 2025
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