Enable A5 remote validation for MX matmul and gemv#836
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zhangstevenunity merged 7 commits intoJun 22, 2026
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This pull request introduces support for the f8E8M0 type (an 8-bit exponent/scale payload type) and its associated layouts (MX_A_ZZ and MX_B_NN) for the Ascend A5 architecture, including updates to layout inference, verifiers, Python/C-API bindings, and EmitC translation. The review feedback highlights opportunities to improve code efficiency and idiomatic usage by replacing string-based type checks with the newly defined isPTOF8E8M0Type helper in InferPTOLayout.cpp and PTOToEmitC.cpp. Additionally, it is recommended to use the defined mValid variable in the verifier within PTO.cpp to maintain consistency.
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Summary发现 2 个问题：A5 TMOV 规范化会不安全地前移 Findings
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A5 板测失败详情：PR #836test_dynamic_valid_shape
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A5 板测失败详情：PR #836xors
xor
vectorAddition
vadd_validshape_hyper
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ttri
trap
trans
tprefetch_async_binding
tprefetch
tpows
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tinsert
tinsert_fp
tileSetGetValue
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test_tmov_row_major_1x16_control_a5
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test_set_wait_unified_api
test_mem_inject_sync_basic
test_intercore_sync_a5
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test_intercore_sync_a5_functional
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test_inject_sync_two_event_id
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test_inject_sync_intra_pipe_barrier
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test_dynamic_valid_shape
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test_a5_buf_sync
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rmsnorm_incore_0
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subview
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subsc
subs
subc
sub
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shrs
shr
shls
shl
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scalar_ptr
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A5 板测失败详情：PR #836rsqrt
rowsum
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bitcast_inplace_cvt
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relu
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post_rmsnorm
out_proj_residual
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vector_example_dag_kernel_mul
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print_scalar
prelu
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plan_memory_peak_8_overlapping
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plan_memory_if_yield
plan_memory_if_in_loop
plan_memory_fragmentation_two_holes
plan_memory_fragmentation_hole_fit
plan_memory_for_iter_args_yield
plan_memory_bind_tile_alias_liveness
partmul
partmin
partmax
partition_view_verify_valid
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partition5d_dynamic_a5
partition5d_a5
partarg
partadd
ors
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A5 板测失败详情：PR #836or
not
neg
muls
mul
mscatter
mrgsort_format2
mrgsort_a5
mins
min
mgather
maxs
max
matmul_mx_low_precision
tmatmulk
matMul
lrelu
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gemvmx
gatherb
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fmods
fmod
fillpad
fillpad_inplace
fillpad_expand
extract_fp
expands
expand
exp
dynamic_tail_matmul
divs2
divs
div
dequant
dequant_i8
sparse_attn_test_incore_7
decode_swa_test_incore_40
decode_hca_test_incore_54
decode_csa_test_incore_81
attention_swa_test_incore_40
attention_hca_test_incore_54
attention_csa_test_refresh_incore_81
tcvt
cvt_f32_f32
cvt_f32_f16
concat
cv_region
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A5 板测失败详情：PR #836twait_atomic_binding
tscatter_root_binding
treduce_root_binding
tnotify_atomic_add_binding
tgather_root_binding
tbroadcast_root_binding
comm_p2p
comm_p2p_binding_variants
comm_collective
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colsum
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ci
bf16_tile
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A5 板测失败详情：PR #836tinsert_fp
test_tmov_row_major_1x16_control_a5
test_tmov_col_major_16x1_align_a5
test_dynamic_valid_shape
test_barrier_sync
test_auto_sync_tail_hint
syncHigh
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rar_optimization_test
nested_loop_confliect
matmul
decode_projection_incore_0
compensation_test
add_double_dynamic
sels
sel
scatter
rowexpandsub
rowexpandmul
rowexpanddiv
rems
rem
rope_kv_cache
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qwen3_decode_incore_7
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qwen3_decode_incore_4
qwen3_decode_incore_2
qwen3_decode_incore_1
qwen3_decode_incore_12
qwen3_decode_incore_11
qwen3_decode_incore_10
post_rmsnorm
vector_example_dag_kernel_mul
vector_example_dag_kernel_add_scalar
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paged_attention_example_kernel_softmax_prepare
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orchestration_example_kernel_mul
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prelu
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partmin
partition_view_verify_valid
partition_view_verify_rank_mismatch_valid
partition5d_dynamic_a5
partition5d_a5
mgather
matmul_mx_low_precision
tensor_view_layout_dn
gemvmx
extract_fp
sparse_attn_test_incore_7
decode_swa_test_incore_40
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decode_csa_test_incore_81
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A5 板测失败详情：PR #836tinsert_fp
tmatmulk_autosync_a5
test_tmov_row_major_1x16_control_a5
test_tmov_col_major_16x1_align_a5
test_dynamic_valid_shape
test_barrier_sync
test_auto_sync_tail_hint
rmsnorm_incore_0
rar_optimization_test
nested_loop_confliect
matmul
decode_projection_incore_0
compensation_test
add_double_dynamic
sels
sel
scatter
rowexpandsub
rowexpandmul
rowexpanddiv
rems
rem
rope_kv_cache
rmsnorm
qwen3_decode_incore_7
qwen3_decode_incore_6
qwen3_decode_incore_5
qwen3_decode_incore_4
qwen3_decode_incore_2
qwen3_decode_incore_1
qwen3_decode_incore_12
qwen3_decode_incore_11
qwen3_decode_incore_10
post_rmsnorm
vector_example_dag_kernel_mul
vector_example_dag_kernel_add_scalar
vector_example_dag_kernel_add
paged_attention_example_kernel_softmax_prepare
paged_attention_example_kernel_qk_matmul
paged_attention_example_kernel_pv_matmul
paged_attention_example_kernel_online_update
paged_attention_example_kernel_init_inplace
orchestration_example_kernel_mul
orchestration_example_kernel_add_scalar
orchestration_example_kernel_add
prelu
plan_memory_reuse_sequential
plan_memory_peak_exact_capacity
plan_memory_peak_8_overlapping
plan_memory_no_reuse_overlap
plan_memory_nested_loops
plan_memory_loop_no_reuse_outer_live
plan_memory_loop_in_if
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plan_memory_fragmentation_two_holes
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plan_memory_bind_tile_alias_liveness
partmin
partition_view_verify_valid
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partition5d_dynamic_a5
partition5d_a5
muls
tensor_view_layout_dn
extract_fp
sparse_attn_test_incore_7
decode_swa_test_incore_40
decode_hca_test_incore_54
decode_csa_test_incore_81
attention_swa_test_incore_40
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Deep correctness pass on the A5 MX matmul/gemv enablement.
The MX feature itself looks solid: the new verifyA5MxGemvScaleTile / TGetScaleAddrOp shape rules are internally consistent with the Gemvmx and MatmulMxLowPrecision samples, and both samples pass the A5 board (absent from the full /run a5 failure list at 070ca6378e5f). One blocking regression plus smaller notes.
Blocking — scalingRoleToken reclassifies all SCALING tiles, breaking non-MX consumers
See the inline comment on PTOToEmitC.cpp. The classification keys off blayout/slayout only, so TInsertFP's f32 scaling fp tile becomes TileType::ScaleLeft and the board fails to compile tinsert_fp (__ca__ float* → __fbuf__ float*). ScaleLeft only exists on this branch ⇒ regression introduced here. Gate the role on an MX-specific signal (!pto.f8E8M0 element type, or use-by tgemv.mx/tmatmul.mx).
On the existing bot comments
- gemini (HIGH ×2) —
isF8E8M0ElemTypeinInferPTOLayout.cpp:89andPTOToEmitC.cpp:508: valid, both should callmlir::pto::isPTOF8E8M0Type()(added in this very PR). The InferPTOLayout copy is worse than "inefficient" —isa<Type>(ty)andty.getTypeID() == ty.getTypeID()are always-true no-ops (dead conditions) wrapped around a fragileos << tystring compare. - gemini (MEDIUM) —
PTO.cpp:7967"mValidis unused": not actionable, appears hallucinated. There is nomValidsymbol anywhere inPTO.cpp; theTGetScaleAddrOpLEFT branch already passessrcValid[0](= valid M), which is correct. Safe to dismiss. - Codex review failed (
exit=1, "review 过程提前失败", no structured findings), so it provided no coverage on this PR.
Minor / non-blocking
TGetScaleAddrOp::verifyLEFT branch derives the scale tile shape cols fromceil(validK/32)(srcValid[1]) but rows from paddedsrcShape[0]. Consistent for the samples (M_pad==M_valid,ceil(110/32)==ceil(128/32)), but can misfire if padded K crosses a 32-boundary above valid K — consider padded K forshape, valid K forvalid_shape. (k/vkin the RIGHT branch are duplicate assignments ofsrcValid[0].)PTOA5NormalizeTMovPasshoiststget_scale_addrbefore its matching scaletmov, but silently skips whenhasInterveningUsesOfDstis true. If the hoist is required for correctness, a skipped case emits the wrong order silently instead of diagnosing — a short comment on why skipping is safe would help.TFillPadOp::getPipe()now returnsPIPE_MTE1for mat→mat purely from address space, with no arch gate; fine for A5 (covered by the new lit test + board), just flagging it would also apply to any A2/A3 mat→mattfillpad.
Positives
extern "C"linkage fix ingenerate_testcase.pycorrectly aligns the launch decl/def (avoids a C++ mangling mismatch).- Replacing
verifyScaleTileMatchesOperandwith compact MX scale semantics is the right modeling call.
(Verdict reflects only the one blocking regression; the rest of the change is in good shape.)
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| return std::string("Tile<") + tileRoleToken(type.getMemorySpace()) + ", " + | ||
| return std::string("Tile<") + | ||
| tileRoleToken(type.getMemorySpace(), type.getConfigAttr()) + ", " + |
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tileRoleToken(type.getMemorySpace(), type.getConfigAttr()) routes every SCALING-space tile through scalingRoleToken, which classifies a tile as TileType::ScaleLeft / ScaleRight purely from its layout (RowMajor/RowMajor → ScaleLeft, ColMajor/ColMajor → ScaleRight). That layout signature is not unique to MX scale tiles, so pre-existing non-MX SCALING tiles get silently reclassified.
Concrete regression (board-confirmed): tinsert_fp. Its fp operand is allocated as scaling, f32, 32x32, blayout=row_major, slayout=row_major (test/samples/TInsert/tinsert_fp.py). On main that lowers to TileType::Scaling (→ __fbuf__); with this change it becomes TileType::ScaleLeft, which maps to a different physical buffer. The A5 board run on this branch (070ca6378e5f) fails to compile it exactly there:
TInsert.hpp:124:93: error: casting '__ca__ float *' to type '__fbuf__ typename
Tile<pto::TileType::ScaleLeft, float, 32, 32, pto::BLayout::RowMajor, 32, 32,
pto::SLayout::RowMajor, 512, ...>::DType *' (aka '__fbuf__ float *')
is not allowed in aicore function
ScaleLeft/ScaleRight only exist on this branch, so this is introduced here (and tinsert_fp is not in DEFAULT_SKIP_CASES). The same unconditional classification is also wired into PointerCastConversion (~L4496) and PTOBindTileToEmitC (~L11619), so any non-MX scaling consumer with these layouts is affected.
Suggested fix: gate the Scale{Left,Right} role on an MX-specific signal rather than layout alone — e.g. the !pto.f8E8M0 element type, or "is consumed as a_scale/b_scale of tgemv.mx/tmatmul.mx" (you already do that style of use-walk for MxValidAlignPolicy). The board MX samples use f8E8M0 scale tiles, so gating on that element type keeps them working while leaving f16/f32 scaling tiles as TileType::Scaling. Also worth adding a lit test that actually CHECKs the ScaleLeft/ScaleRight token — none of the current EmitC tests assert it.
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Cross-checked against the lower-layer pto-isa (the pinned 66c931430f; verified the same symbols in PTO-ISA/pto-isa). To be clear this is a "gate it", not a "drop it" comment — the new !pto.f8E8M0 type and MX_A_ZZ/MX_B_NN layouts are genuinely required by pto-isa:
include/pto/npu/a5/TLoad.hpphard-asserts the scale payload type:Sostatic_assert(caps::IsFP8E8M0<typename TileData::DType>() && caps::IsFP8E8M0<typename GlobalData::RawDType>(), "Fix: DType only support float8_e8m0_t in MX_A_ZZ or MX_B_NN");
!pto.f8E8M0<->float8_e8m0_t, and theMX_A_ZZ/MX_B_NNlayouts (consumed byTileShape2D/BaseShape2D<..., Layout::MX_A_ZZ>for the[16,2]compact fractal) are mandatory to even compile an MX scaleTLoad. Those additions are correct.
What makes the tinsert_fp failure a regression (not a missing feature) is only the role->buffer mapping, from include/pto/common/buffer_limits.hpp + memory.hpp:
| TileType | Physical buffer |
|---|---|
ScaleLeft |
L0A (A5-only cube buffer) |
ScaleRight |
L0B (A5-only cube buffer) |
Scaling |
__fbuf__ |
They are physically distinct buffers, so classifying a non-MX Scaling tile as ScaleLeft relocates it from __fbuf__ to L0A — exactly the __ca__ float* -> __fbuf__ float* cast error on TInsertFP's f32 fp tile.
pto-isa itself points to the precise fix: since MX scales must be float8_e8m0_t, gate the ScaleLeft/ScaleRight role on the f8E8M0 element type (or on "consumed as a_scale/b_scale of tgemv.mx/tmatmul.mx"). That also makes this path consistent with InferPTOLayout, which already gates MX-layout inference on isF8E8M0ElemType — today the layout path is e8m0-gated but the tile-role path is layout-only. After gating, the f32 fp tile stays Scaling/__fbuf__ and the MX scales (always e8m0) still resolve to ScaleLeft/ScaleRight:
static const char *scalingRoleToken(pto::TileBufConfigAttr configAttr, Type elemTy) {
if (!isF8E8M0ElemType(elemTy)) // non-MX scaling tiles (e.g. TInsertFP fp) stay in __fbuf__
return "TileType::Scaling";
pto::BLayout bl = getTileBufBLayoutValue(configAttr);
pto::SLayout sl = getTileBufSLayoutValue(configAttr);
if (bl == pto::BLayout::RowMajor && sl == pto::SLayout::RowMajor) return "TileType::ScaleLeft";
if (bl == pto::BLayout::ColMajor && sl == pto::SLayout::ColMajor) return "TileType::ScaleRight";
return "TileType::Scaling";
}(thread elemTy through the three call sites: getEmitCTileTypeString L833, PointerCastConversion ~L4496, PTOBindTileToEmitC ~L11619 — the tile element type is already available at each.)
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已按gate的方式处理，补充相关lit
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d777d50f resolves this correctly. ✅
scalingRoleTokenis now gated onisF8E8M0ElemType(elemTy)(returnsTileType::Scalingotherwise), andelemTyis threaded through all three call sites —getEmitCTileTypeString(L833),PointerCastConversion(L4496),PTOBindTileToEmitC(L11620). MX scales stayScaleLeft/ScaleRightbecause pto-isa mandates they befloat8_e8m0_t, so the gate never excludes them.- The new
test/lit/pto/tinsert_fp_scaling_tile_role_emitc.ptolocks the regression:CHECK: Tile<TileType::Scaling, float, 32, 32+CHECK-NOT: Tile<TileType::ScaleLeft, ...>. That's exactly the missing coverage. 👍
Two follow-ups:
- Consistency (gemini's other HIGH): the identical helper in
lib/PTO/Transforms/InferPTOLayout.cpp:79was not touched — it still uses theos << tystring compare plus the always-trueisa<Type>(ty)andty.getTypeID() == ty.getTypeID()conditions. Same one-liner applies:return mlir::pto::isPTOF8E8M0Type(ty);. Worth folding in here since you just fixed thePTOToEmitC.cpptwin. - Board reconfirm: the latest A5 board run is still on
070ca6378e5f(pre-fix). A/run a5ond777d50fwould confirmtinsert_fpcompiles again (the__ca__→__fbuf__error is gone).
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A5 板测失败
失败用例
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A5 板测失败详情：PR #836test_tmov_row_major_1x16_control_a5
test_tmov_col_major_16x1_align_a5
test_dynamic_valid_shape
test_barrier_sync
test_auto_sync_tail_hint
rmsnorm_incore_0
rar_optimization_test
nested_loop_confliect
matmul
decode_projection_incore_0
compensation_test
add_double_dynamic
sels
sel
scatter
rowexpandsub
rowexpandmul
rowexpanddiv
rems
rem
rope_kv_cache
rmsnorm
qwen3_decode_incore_7
qwen3_decode_incore_6
qwen3_decode_incore_5
qwen3_decode_incore_4
qwen3_decode_incore_2
qwen3_decode_incore_1
qwen3_decode_incore_12
qwen3_decode_incore_11
qwen3_decode_incore_10
post_rmsnorm
vector_example_dag_kernel_mul
vector_example_dag_kernel_add_scalar
vector_example_dag_kernel_add
paged_attention_example_kernel_softmax_prepare
paged_attention_example_kernel_qk_matmul
paged_attention_example_kernel_pv_matmul
paged_attention_example_kernel_online_update
paged_attention_example_kernel_init_inplace
orchestration_example_kernel_mul
orchestration_example_kernel_add_scalar
orchestration_example_kernel_add
prelu
plan_memory_reuse_sequential
plan_memory_peak_exact_capacity
plan_memory_peak_8_overlapping
plan_memory_no_reuse_overlap
plan_memory_nested_loops
plan_memory_loop_no_reuse_outer_live
plan_memory_loop_in_if
plan_memory_if_yield
plan_memory_if_in_loop
plan_memory_fragmentation_two_holes
plan_memory_fragmentation_hole_fit
plan_memory_for_iter_args_yield
plan_memory_bind_tile_alias_liveness
partmin
partition_view_verify_valid
partition_view_verify_rank_mismatch_valid
partition5d_dynamic_a5
partition5d_a5
tensor_view_layout_dn
extract_fp
sparse_attn_test_incore_7
decode_swa_test_incore_40
decode_hca_test_incore_54
decode_csa_test_incore_81
attention_swa_test_incore_40
attention_hca_test_incore_54
attention_csa_test_refresh_incore_81
tbroadcast_root_binding
cmps
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Summary
tgemv.mx*andtget_scale_addr, instead of requiring scale tiles to match operand shapesGemvmxandMatmulMxLowPrecision, and update validation helpers for float8 payloads and the pinnedpto-isarevisionValidation
build-local-vpto/tools/ptoas/ptoas --pto-arch=a5 test/samples/Gemvmx/gemvmx-pto.pto -o /tmp/gemvmx-pto.cppbuild-local-vpto/tools/ptoas/ptoas --pto-arch=a5 test/samples/MatmulMxLowPrecision/matmul_mx_low_precision-pto.pto -o /tmp/matmul_mx_low_precision-pto.cpp/Users/jimmychou/work/ptoas/llvm-workspace/llvm-project/build-release/bin/llvm-lit /Users/jimmychou/work/ptoas/PTOAS-main-latest/build-local-vpto/test/lit/lit.site.cfg.py test/lit/pto/tgemv_mx_emitc.pto test/lit/pto/tgemv_mx_accphase_emitc.pto test/lit/pto/tgemv_mx_f8e5m2_emitc.pto test/lit/pto/tgemv_mx_variants_emitc.pto test/lit/pto/tget_scale_addr_emitc.pto test/lit/pto/tget_scale_addr_verify_invalid.ptoRelated to #810.