Verilog-SystemVerilog

This Repo contains some of my Verilog & SystemVerilog Programs.

Name		Name	Last commit message	Last commit date
Latest commit History 26 Commits
Async FIFO		Async FIFO
Dual_Port		Dual_Port
FIFO		FIFO
Flipflops		Flipflops
Gates		Gates
Interrupt_controller		Interrupt_controller
Memory		Memory
Memory_Wrapper		Memory_Wrapper
PISO		PISO
SPI		SPI
Watchdog_Timer		Watchdog_Timer
README.md		README.md

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