@@ -773,94 +773,90 @@ int32_t lis2mdl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
773773}
774774
775775/**
776- * @brief Software reset. Restore the default values in user registers.[set]
776+ * @brief Software reset. Restore the default values in user registers.
777777 *
778778 * @param ctx read / write interface definitions.(ptr)
779- * @param val change the values of soft_rst in reg CFG_REG_A
780779 * @retval interface status.(MANDATORY: return 0 -> no Error)
781780 *
782781 */
783- int32_t lis2mdl_reset_set (const stmdev_ctx_t * ctx , uint8_t val )
782+ int32_t lis2mdl_sw_reset (const stmdev_ctx_t * ctx )
784783{
785- lis2mdl_cfg_reg_a_t reg ;
784+ lis2mdl_cfg_reg_a_t reg = {0 };
785+ uint8_t retry = {0 };
786786 int32_t ret ;
787787
788- ret = lis2mdl_read_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
789-
790- if (ret == 0 )
788+ if (ctx -> mdelay == NULL )
791789 {
792- reg . soft_rst = val ;
793- ret = lis2mdl_write_reg ( ctx , LIS2MDL_CFG_REG_A , ( uint8_t * ) & reg , 1 ) ;
790+ ret = -1 ;
791+ goto exit ;
794792 }
795793
796- return ret ;
797- }
794+ /* 1. Set the SOFT_RST bit of the CFG_REG_A register to 1. */
795+ reg .soft_rst = 1 ;
796+ ret = lis2mdl_write_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
798797
799- /**
800- * @brief Software reset. Restore the default values in user registers.[get]
801- *
802- * @param ctx read / write interface definitions.(ptr)
803- * @param val change the values of soft_rst in reg CFG_REG_A.(ptr)
804- * @retval interface status.(MANDATORY: return 0 -> no Error)
805- *
806- */
807- int32_t lis2mdl_reset_get (const stmdev_ctx_t * ctx , uint8_t * val )
808- {
809- lis2mdl_cfg_reg_a_t reg ;
810- int32_t ret ;
798+ if (ret != 0 )
799+ {
800+ goto exit ;
801+ }
811802
812- ret = lis2mdl_read_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
803+ /* 2. Poll the SOFT_RST bit of the CFG_REG_A register until it returns
804+ * to 0. (should require 5us) */
805+ do {
806+ ret += lis2mdl_read_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
813807
814- if (ret != 0 ) { return ret ; }
808+ if (ret != 0 )
809+ {
810+ goto exit ;
811+ }
812+
813+ ctx -> mdelay (1 );
814+ } while (reg .soft_rst == 1 && retry ++ < 3 );
815815
816- * val = reg .soft_rst ;
816+ return ( reg .soft_rst == 0 ) ? 0 : -1 ;
817817
818+ exit :
818819 return ret ;
819820}
820821
821822/**
822- * @brief Reboot memory content. Reload the calibration parameters.[set]
823+ * @brief Reboot memory content. Reload the calibration paramters.
824+ * (20 ms boot procedure)
823825 *
824826 * @param ctx read / write interface definitions.(ptr)
825- * @param val change the values of reboot in reg CFG_REG_A
826827 * @retval interface status.(MANDATORY: return 0 -> no Error)
827828 *
828829 */
829- int32_t lis2mdl_boot_set (const stmdev_ctx_t * ctx , uint8_t val )
830+ int32_t lis2mdl_reboot (const stmdev_ctx_t * ctx )
830831{
831832 lis2mdl_cfg_reg_a_t reg ;
832833 int32_t ret ;
833834
835+ if (ctx -> mdelay == NULL ) {
836+ ret = -1 ;
837+ goto exit ;
838+ }
839+
834840 ret = lis2mdl_read_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
835841
836- if (ret = = 0 )
842+ if (ret ! = 0 )
837843 {
838- reg .reboot = val ;
839- ret = lis2mdl_write_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
844+ goto exit ;
840845 }
841846
842- return ret ;
843- }
847+ /* 1. Set the REBOOT bit of the CFG_REG_A register to 1. */
848+ reg .reboot = 1 ;
849+ ret = lis2mdl_write_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
844850
845- /**
846- * @brief Reboot memory content. Reload the calibration parameters.[get]
847- *
848- * @param ctx read / write interface definitions.(ptr)
849- * @param val change the values of reboot in reg CFG_REG_A.(ptr)
850- * @retval interface status.(MANDATORY: return 0 -> no Error)
851- *
852- */
853- int32_t lis2mdl_boot_get (const stmdev_ctx_t * ctx , uint8_t * val )
854- {
855- lis2mdl_cfg_reg_a_t reg ;
856- int32_t ret ;
857-
858- ret = lis2mdl_read_reg (ctx , LIS2MDL_CFG_REG_A , (uint8_t * )& reg , 1 );
859-
860- if (ret != 0 ) { return ret ; }
851+ if (ret != 0 )
852+ {
853+ goto exit ;
854+ }
861855
862- * val = reg .reboot ;
856+ /* 2. Wait 20 ms for boot time */
857+ ctx -> mdelay (20 );
863858
859+ exit :
864860 return ret ;
865861}
866862
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