This repostory contains the verilog codes for the labs that I have performed in Digital System Design course.

Name		Name	Last commit message	Last commit date
Latest commit History 23 Commits
Lab 1.srcs		Lab 1.srcs
Lab 2.srcs		Lab 2.srcs
Lab 4.srcs		Lab 4.srcs
Lab 5.srcs		Lab 5.srcs
Lab4.srcs		Lab4.srcs
Lab_3.srcs		Lab_3.srcs
Project.srcs		Project.srcs
UART_VERILOG		UART_VERILOG
LICENSE		LICENSE
README.md		README.md

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