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danielinuxdanielinux
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Added support for ATMEL SAM-R21
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‎hal/samr21.c‎

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/* samr21.c
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*
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* Copyright (C) 2018 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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/* Clock settings for cpu samd21g18a @ 48MHz */
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#define CPU_FREQ (48000000)
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#define GCLK_CTRL_RESET (1)
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#define GCLK_GENDIV_DIVSHIFT (8)
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#define GCLK_CLKCTRL_GENSHIFT (8)
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#define GCLK_STATUS_SYNCBUSY (1 << 7)
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#define GCLK_GENCTRL_SRC_OSC8M (6 << 8)
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#define GCLK_GENCTRL_EN (1 << 16)
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#define GCLK_GENCTRL_SRC_FDPLL (1 << 11)
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#define GCLK_CLKCTRL_GEN_CLK7 (7 << 8)
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#define GCLK_CLKCTRL_CLKEN (1 << 14)
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#define WAITSTATES (1)
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/* Flash settings for samd21g18a */
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#define FLASH_SIZE (256 * 1024)
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#define FLASH_PAGESIZE 64
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#define FLASH_N_PAGES 4096
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#define WDT_CTRL *((volatile uint8_t *)(0x40001000))
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#define WDT_EN (1 << 1)
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#define APBAMASK_REG *((volatile uint32_t *)(0x40000418))
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#define APBAMASK_PM_EN (1 << 1)
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#define APBAMASK_SYSCTRL_EN (1 << 2)
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#define APBAMASK_GCLK_EN (1 << 3)
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#define APBBMASK_REG *((volatile uint32_t *)(0x4000041C))
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#define APBBMASK_NVM_EN (1 << 2)
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#define NVMCTRL_BASE (0x41004000)
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#define NVMCTRLA_REG *((volatile uint16_t *)(NVMCTRL_BASE))
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#define NVMCTRLB_REG *((volatile uint32_t *)(NVMCTRL_BASE + 4))
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#define NVMCTRL_INTFLAG *((volatile uint8_t *)(NVMCTRL_BASE + 0x14))
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#define NVMCTRL_ADDR *((volatile uint32_t *)(NVMCTRL_BASE + 0x1c))
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#define NVMCMD_KEY (0xA500)
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#define NVMCMD_ERASE (0x02)
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#define NVMCMD_WP (0x04)
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#define NVMCMD_PBC (0x44)
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#define NVMCTRL_INTFLAG_NVMREADY (1)
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#define GCLK_BASE (0x40000C00)
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#define GCLK_CTRL *((volatile uint8_t *)(GCLK_BASE))
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#define GCLK_STATUS *((volatile uint8_t *)(GCLK_BASE + 1))
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#define GCLK_CLKCTRL *((volatile uint16_t *)(GCLK_BASE + 2))
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#define GCLK_GENCTRL *((volatile uint32_t *)(GCLK_BASE + 4))
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#define GCLK_GENDIV *((volatile uint32_t *)(GCLK_BASE + 8))
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#define SYSCTRL_OSC8M *((volatile uint32_t *)(0x40000820))
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#define SYSCTRL_OSC8M_ENABLE (1 << 1)
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#define SYSCTRL_OSC8M_ONDEMAND (1 << 7)
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#define SYSCTRL_OSC8M_PRESC_MASK (3 << 8)
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#define SYSCTRL_OSC8M_RUNSTDBY (1 << 6)
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#define SYSCTRL_PLLK_SR *((volatile uint32_t *)(0x4000080c))
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#define PLLK_SR_OSC8M_RDY (1 << 3)
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#define OSC8M_WAITBUSY() { while (!(SYSCTRL_PLLK_SR & (PLLK_SR_OSC8M_RDY))) {} }
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#define SYSCTRL_DPLL (0x40000844)
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#define SYSCTRL_DPLLCTRLA *((volatile uint8_t *)(0x40000844))
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#define SYSCTRL_DPLLRATIO *((volatile uint32_t *)(0x40000848))
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#define SYSCTRL_DPLLCTRLB *((volatile uint32_t *)(0x4000084C))
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#define SYSCTRL_DPLLSTATUS *((volatile uint8_t *)(0x40000850))
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#define DPLLCTRLA_ENABLE (1 << 1)
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#define DPLLCTRLB_REFCLK_GCLK (1 << 5)
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#define DPLLSTATUS_CLKRDY (1 << 1)
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#define DPLLSTATUS_LOCK (1 << 0)
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#define SYSCTRL_DPLLSTATUS_WAITLOCK() { while (!(SYSCTRL_DPLLSTATUS & (DPLLSTATUS_CLKRDY | DPLLSTATUS_LOCK))) {} }
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#define PAC1_BASE (0x41000000)
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#define PAC1_WPCLR *((volatile uint32_t *)(PAC1_BASE)) /* Register to clear write protection (unlock flash) */
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#define PAC1_WPSET *((volatile uint32_t *)(PAC1_BASE + 4)) /* Register to set write protection (lock flash) */
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#define PAC_WP_NVMCTL (1 << 1) /* Bit position for NVM in WPCLR/WPSET registers */
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#define GCLK_WAITBUSY() { while (GCLK_STATUS & GCLK_STATUS_SYNCBUSY) {} }
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void hal_init(void)
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{
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WDT_CTRL &= (~WDT_EN);
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__asm__ volatile ("cpsid i");
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uint32_t i, reg;
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/* enable clocks for the power, sysctrl and gclk modules */
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APBAMASK_REG = APBAMASK_PM_EN | APBAMASK_SYSCTRL_EN | APBAMASK_GCLK_EN;
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/* set NVM wait states */
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APBBMASK_REG |= APBBMASK_NVM_EN;
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NVMCTRLB_REG |= ((WAITSTATES & 0x0f) << 1);
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APBBMASK_REG &= ~APBBMASK_NVM_EN;
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/* Set 8MHz oscillator */
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reg = SYSCTRL_OSC8M & (~(SYSCTRL_OSC8M_PRESC_MASK | SYSCTRL_OSC8M_RUNSTDBY));
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SYSCTRL_OSC8M = reg | SYSCTRL_OSC8M_ENABLE | SYSCTRL_OSC8M_ONDEMAND;
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OSC8M_WAITBUSY();
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/* Set PLL config */
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GCLK_CTRL = GCLK_CTRL_RESET;
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GCLK_WAITBUSY();
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GCLK_GENDIV = (8 << GCLK_GENDIV_DIVSHIFT) | 1;
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GCLK_GENCTRL = GCLK_GENCTRL_EN | GCLK_GENCTRL_SRC_OSC8M | 1;
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GCLK_CLKCTRL = (1 << GCLK_CLKCTRL_GENSHIFT) | GCLK_CLKCTRL_CLKEN | 1;
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GCLK_WAITBUSY();
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SYSCTRL_DPLLRATIO = (47);
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SYSCTRL_DPLLCTRLB = DPLLCTRLB_REFCLK_GCLK;
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SYSCTRL_DPLLCTRLA = DPLLCTRLA_ENABLE;
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SYSCTRL_DPLLSTATUS_WAITLOCK();
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GCLK_GENDIV = (1 << GCLK_GENDIV_DIVSHIFT) | 0;
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GCLK_GENCTRL = GCLK_GENCTRL_EN | GCLK_GENCTRL_SRC_FDPLL;
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GCLK_WAITBUSY();
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for (i = 3; i <= 34; i++) {
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GCLK_CLKCTRL = GCLK_CLKCTRL_GEN_CLK7 | i;
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GCLK_WAITBUSY();
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}
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}
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void hal_prepare_boot(void)
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{
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/* Reset NVM wait states */
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APBBMASK_REG |= APBBMASK_NVM_EN;
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NVMCTRLB_REG &= ~((WAITSTATES & 0x0f) << 1);
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APBBMASK_REG &= ~APBBMASK_NVM_EN;
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/* Reset clock controller */
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GCLK_CTRL = GCLK_CTRL_RESET;
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GCLK_WAITBUSY();
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}
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int hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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int i = 0;
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uint32_t *src, *dst;
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if (len <= 0)
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return 0;
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/* Clear page buffer */
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NVMCTRLA_REG = (NVMCMD_PBC | NVMCMD_KEY);
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while (i < len) {
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if ((len - i > 3) && ((((address + i) & 0x03) == 0) && ((((uint32_t)data) + i) & 0x03) == 0)) {
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src = (uint32_t *)data;
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dst = (uint32_t *)address;
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dst[i >> 2] = src[i >> 2];
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i+=4;
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} else {
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uint32_t val;
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uint8_t *vbytes = (uint8_t *)(&val);
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int off = (address + i) - (((address + i) >> 2) << 2);
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dst = (uint32_t *)(address - off);
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val = dst[i >> 2];
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vbytes[off] = data[i];
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dst[i >> 2] = val;
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i++;
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}
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}
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/* Enable write protection */
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NVMCTRLA_REG = (NVMCMD_WP | NVMCMD_KEY);
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return 0;
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}
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void hal_flash_unlock(void)
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{
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PAC1_WPCLR |= (PAC_WP_NVMCTL);
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}
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void hal_flash_lock(void)
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{
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PAC1_WPSET |= (PAC_WP_NVMCTL);
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}
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int hal_flash_erase(uint32_t address, int len)
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{
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while (len > 0) {
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NVMCTRL_ADDR = (address >> 1); /* This register holds the address of a 16-bit row */
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NVMCTRLA_REG = NVMCMD_ERASE | NVMCMD_KEY;
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while(!(NVMCTRL_INTFLAG & NVMCTRL_INTFLAG_NVMREADY))
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len -= FLASH_PAGESIZE;
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}
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return 0;
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}
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‎hal/samr21.ld‎

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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x0010000
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
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}
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.isr_vector))
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*(.text*)
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*(.rodata*)
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*(.init*)
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*(.fini*)
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. = ALIGN(4);
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_end_text = .;
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} > FLASH
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.edidx :
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{
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. = ALIGN(4);
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*(.ARM.exidx*)
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} > FLASH
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_stored_data = .;
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.data : AT (_stored_data)
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{
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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_end_data = .;
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} > RAM
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.bss (NOLOAD) :
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{
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_start_bss = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_end_bss = .;
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__bss_end__ = .;
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_end = .;
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} > RAM
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. = ALIGN(4);
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}
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END_STACK = ORIGIN(RAM) + LENGTH(RAM);

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