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danielinuxdanielinux
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Lines changed: 136 additions & 114 deletions

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‎config/examples/sama5d3.config‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ ARCH?=ARM
22
TARGET?=sama5d3
33
SIGN?=ECC256
44
HASH?=SHA256
5-
DEBUG?=1
5+
DEBUG?=0
66
VTOR?=1
77
CORTEX_M0?=0
88
NO_ASM?=0

‎hal/sama5d3.c‎

Lines changed: 85 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -32,82 +32,82 @@ void sleep_us(uint32_t usec);
3232

3333
/* Manual division operation */
3434
static int division(uint32_t dividend,
35-
uint32_t divisor,
36-
uint32_t *quotient,
37-
uint32_t *remainder)
38-
{
39-
uint32_t shift;
40-
uint32_t divisor_shift;
41-
uint32_t factor = 0;
42-
unsigned char end_flag = 0;
43-
44-
if (!divisor)
45-
return 0xffffffff;
46-
47-
if (dividend < divisor) {
48-
*quotient = 0;
49-
*remainder = dividend;
50-
return 0;
51-
}
35+
uint32_t divisor,
36+
uint32_t *quotient,
37+
uint32_t *remainder)
38+
{
39+
uint32_t shift;
40+
uint32_t divisor_shift;
41+
uint32_t factor = 0;
42+
unsigned char end_flag = 0;
43+
44+
if (!divisor)
45+
return 0xffffffff;
46+
47+
if (dividend < divisor) {
48+
*quotient = 0;
49+
*remainder = dividend;
50+
return 0;
51+
}
5252

53-
while (dividend >= divisor) {
54-
for (shift = 0, divisor_shift = divisor;
55-
dividend >= divisor_shift;
56-
divisor_shift <<= 1, shift++) {
57-
if (dividend - divisor_shift < divisor_shift) {
58-
factor += 1 << shift;
59-
dividend -= divisor_shift;
60-
end_flag = 1;
61-
break;
62-
}
63-
}
53+
while (dividend >= divisor) {
54+
for (shift = 0, divisor_shift = divisor;
55+
dividend >= divisor_shift;
56+
divisor_shift <<= 1, shift++) {
57+
if (dividend - divisor_shift < divisor_shift) {
58+
factor += 1 << shift;
59+
dividend -= divisor_shift;
60+
end_flag = 1;
61+
break;
62+
}
63+
}
6464

65-
if (end_flag)
66-
continue;
65+
if (end_flag)
66+
continue;
6767

68-
factor += 1 << (shift - 1);
69-
dividend -= divisor_shift >> 1;
70-
}
68+
factor += 1 << (shift - 1);
69+
dividend -= divisor_shift >> 1;
70+
}
7171

72-
if (quotient)
73-
*quotient = factor;
72+
if (quotient)
73+
*quotient = factor;
7474

75-
if (remainder)
76-
*remainder = dividend;
75+
if (remainder)
76+
*remainder = dividend;
7777

78-
return 0;
78+
return 0;
7979
}
8080

8181
static uint32_t div(uint32_t dividend, uint32_t divisor)
8282
{
83-
uint32_t quotient = 0;
84-
uint32_t remainder = 0;
85-
int ret;
83+
uint32_t quotient = 0;
84+
uint32_t remainder = 0;
85+
int ret;
8686

87-
ret = division(dividend, divisor, &quotient, &remainder);
88-
if (ret)
89-
return 0xffffffff;
87+
ret = division(dividend, divisor, &quotient, &remainder);
88+
if (ret)
89+
return 0xffffffff;
9090

91-
return quotient;
91+
return quotient;
9292
}
9393

9494
static uint32_t mod(uint32_t dividend, uint32_t divisor)
9595
{
96-
uint32_t quotient = 0;
97-
uint32_t remainder = 0;
98-
int ret;
96+
uint32_t quotient = 0;
97+
uint32_t remainder = 0;
98+
int ret;
9999

100-
ret = division(dividend, divisor, &quotient, &remainder);
101-
if (ret)
102-
return 0xffffffff;
100+
ret = division(dividend, divisor, &quotient, &remainder);
101+
if (ret)
102+
return 0xffffffff;
103103

104-
return remainder;
104+
return remainder;
105105
}
106106

107107
/* RAM configuration: 2 x MT47H64M16 on SAMA5D3-Xplained
108108
* 8 Mwords x 8 Banks x 16 bits x 2, total 2 Gbit
109109
*/
110-
static struct dram ddram ={
110+
static const struct dram ddram ={
111111
.timing = { /* Hardcoded for MT47H64M16, */
112112
.tras = 6,
113113
.trcd = 2,
@@ -132,7 +132,7 @@ static struct dram ddram ={
132132

133133
void master_clock_set(uint32_t prescaler)
134134
{
135-
uint32_t mck = PMC_MCKR & (PMC_MDIV_MASK | PMC_CSS_MASK);
135+
uint32_t mck = PMC_MCKR & (PMC_MDIV_MASK | PMC_CSS_MASK);
136136
uint32_t diff = mck ^ prescaler;
137137

138138
if (diff & PMC_ALTPRES_MASK) {
@@ -262,7 +262,6 @@ static void ddr_init(void)
262262
cal &= ~(MPDDRC_IOCALIBR_RDIV_MASK);
263263
cal |= MPDDRC_IOCALIBR_RDIV_DDR2_RZQ_50; /* 50 ohm */
264264
cal &= ~(MPDDRC_IOCALIBR_TZQIO_MASK);
265-
//cal |= (80 << MPDDRC_IOCALIBR_TZQIO_SHIFT); /* 100 cycles at 133MHz is 0.75 us, 100 cycles at 166MHz is 0.6 us */
266265
cal |= (100 << MPDDRC_IOCALIBR_TZQIO_SHIFT); /* 100 cycles at 133MHz is 0.75 us, 100 cycles at 166MHz is 0.6 us */
267266

268267
MPDDRC_IO_CALIBR = cal;
@@ -608,7 +607,7 @@ int ext_flash_read(uintptr_t address, uint8_t *data, int len)
608607
sz = remaining;
609608

610609
do {
611-
ret = nand_check_bad_block(block);
610+
ret = nand_check_bad_block(block);
612611
if (ret < 0) {
613612
/* Block is bad, skip it */
614613
block++;
@@ -661,35 +660,39 @@ void pit_init(void)
661660

662661
void sleep_us(uint32_t usec)
663662
{
664-
uint32_t base = PIT_PIIR;
665-
uint32_t delay;
666-
uint32_t current;
667-
668-
/* Since our division function which costs much run time
669-
* causes the delay time error.
670-
* So here using shifting to implement the division.
671-
* to change "1000" to "1024", this cause some inaccuacy,
672-
* but it is acceptable.
673-
* ((MASTER_CLOCK / 1024) * usec) / (16 * 1024)
674-
*/
663+
uint32_t base = PIT_PIIR;
664+
uint32_t delay;
665+
uint32_t current;
666+
667+
/* Since our division function which costs much run time
668+
* causes the delay time error.
669+
* So here using shifting to implement the division.
670+
* to change "1000" to "1024", this cause some inaccuacy,
671+
* but it is acceptable.
672+
* ((MASTER_CLOCK / 1024) * usec) / (16 * 1024)
673+
*/
675674
delay = ((MASTER_FREQ >> 10) * usec) >> 14;
676-
do {
677-
current = PIT_PIIR;
678-
current -= base;
679-
} while (current < delay);
675+
do {
676+
current = PIT_PIIR;
677+
current -= base;
678+
} while (current < delay);
680679
}
681680

682-
683-
684-
685-
686681
int ext_flash_write(uintptr_t address, const uint8_t *data, int len)
687682
{
683+
/* TODO */
684+
(void)address;
685+
(void)data;
686+
(void)len;
687+
688688
return 0;
689689
}
690690

691691
int ext_flash_erase(uintptr_t address, int len)
692692
{
693+
/* TODO */
694+
(void)address;
695+
(void)len;
693696
return 0;
694697
}
695698

@@ -704,22 +707,12 @@ void ext_flash_lock(void)
704707

705708
void* hal_get_dts_address(void)
706709
{
707-
return (void*)&dts_addr;
710+
return (void*)&dts_addr;
708711
}
709712

710713
void* hal_get_dts_update_address(void)
711714
{
712-
return NULL; /* Not yet supported */
713-
}
714-
715-
/* QSPI functions */
716-
void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
717-
{
718-
}
719-
720-
721-
void zynq_init(uint32_t cpu_clock)
722-
{
715+
return NULL; /* Not yet supported */
723716
}
724717

725718

@@ -740,6 +733,9 @@ void hal_prepare_boot(void)
740733

741734
int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
742735
{
736+
(void)address;
737+
(void)data;
738+
(void)len;
743739
return 0;
744740
}
745741

@@ -754,6 +750,8 @@ void RAMFUNCTION hal_flash_lock(void)
754750

755751
int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
756752
{
753+
(void)address;
754+
(void)len;
757755
return 0;
758756
}
759757

‎hal/sama5d3.h‎

Lines changed: 48 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,35 @@
1+
/* sama5d3.h
2+
*
3+
* Header file for SAMA5D3 HAL
4+
*
5+
* Copyright (C) 2024 wolfSSL Inc.
6+
*
7+
* This file is part of wolfBoot.
8+
*
9+
* wolfBoot is free software; you can redistribute it and/or modify
10+
* it under the terms of the GNU General Public License as published by
11+
* the Free Software Foundation; either version 3 of the License, or
12+
* (at your option) any later version.
13+
*
14+
* wolfBoot is distributed in the hope that it will be useful,
15+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
16+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17+
* GNU General Public License for more details.
18+
*
19+
* You should have received a copy of the GNU General Public License
20+
* along with this program; if not, write to the Free Software
21+
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
22+
*/
123

224
#ifndef SAMA5D3_HAL_H
325
#define SAMA5D3_HAL_H
426

527
#include <stdint.h>
628

729
/* CPU/Board clock settings */
8-
#define CPU_FREQ 264000000
9-
#define MASTER_FREQ 132000000
10-
#define CRYSTAL_FREQ 12000000
30+
#define CPU_FREQ 264000000UL
31+
#define MASTER_FREQ 132000000UL
32+
#define CRYSTAL_FREQ 12000000UL
1133
#define MULA 43
1234

1335
/* PLLA register
@@ -309,11 +331,11 @@ extern void *kernel_addr, *update_addr, *dts_addr;
309331
#define NAND_FLASH_OOB_SIZE 0x40 /* 64B */
310332

311333
/* Address space mapping for atsama5d3 */
312-
#define DRAM_BASE 0x20000000
313-
#define CS1_BASE 0x40000000
314-
#define CS2_BASE 0x50000000
315-
#define CS3_BASE 0x60000000
316-
#define NFC_CMD_BASE 0x70000000
334+
#define DRAM_BASE 0x20000000UL
335+
#define CS1_BASE 0x40000000UL
336+
#define CS2_BASE 0x50000000UL
337+
#define CS3_BASE 0x60000000UL
338+
#define NFC_CMD_BASE 0x70000000UL
317339

318340
/* NAND flash is mapped to CS3 */
319341
#define NAND_BASE CS3_BASE
@@ -405,4 +427,22 @@ extern void *kernel_addr, *update_addr, *dts_addr;
405427
#define MAX_ECC_BYTES 8
406428
#endif
407429

430+
#define GPIOE_BASE 0xFFFFFA00
431+
432+
#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00)
433+
#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04)
434+
#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08)
435+
#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10)
436+
#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14)
437+
#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18)
438+
#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30)
439+
#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34)
440+
#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40)
441+
#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44)
442+
#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50)
443+
#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54)
444+
#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60)
445+
#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64)
446+
447+
408448
#endif

‎test-app/app_sama5d3.c‎

Lines changed: 2 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
*
33
* Test bare-metal boot application
44
*
5-
* Copyright (C) 2021 wolfSSL Inc.
5+
* Copyright (C) 2024 wolfSSL Inc.
66
*
77
* This file is part of wolfBoot.
88
*
@@ -24,29 +24,13 @@
2424
#include <stdlib.h>
2525
#include <stdint.h>
2626
#include <string.h>
27+
#include <hal/sama5d3.h>
2728

2829
#include "wolfboot/wolfboot.h"
2930

3031
#ifdef TARGET_sama5d3
3132
/* Blue LED is PE23, Red LED is PE24 */
3233

33-
#define GPIOE_BASE 0xFFFFFA00
34-
35-
#define GPIOE_PER *(volatile uint32_t *)(GPIOE_BASE + 0x00)
36-
#define GPIOE_PDR *(volatile uint32_t *)(GPIOE_BASE + 0x04)
37-
#define GPIOE_PSR *(volatile uint32_t *)(GPIOE_BASE + 0x08)
38-
#define GPIOE_OER *(volatile uint32_t *)(GPIOE_BASE + 0x10)
39-
#define GPIOE_ODR *(volatile uint32_t *)(GPIOE_BASE + 0x14)
40-
#define GPIOE_OSR *(volatile uint32_t *)(GPIOE_BASE + 0x18)
41-
#define GPIOE_SODR *(volatile uint32_t *)(GPIOE_BASE + 0x30)
42-
#define GPIOE_CODR *(volatile uint32_t *)(GPIOE_BASE + 0x34)
43-
#define GPIOE_IER *(volatile uint32_t *)(GPIOE_BASE + 0x40)
44-
#define GPIOE_IDR *(volatile uint32_t *)(GPIOE_BASE + 0x44)
45-
#define GPIOE_MDER *(volatile uint32_t *)(GPIOE_BASE + 0x50)
46-
#define GPIOE_MDDR *(volatile uint32_t *)(GPIOE_BASE + 0x54)
47-
#define GPIOE_PPUDR *(volatile uint32_t *)(GPIOE_BASE + 0x60)
48-
#define GPIOE_PPUER *(volatile uint32_t *)(GPIOE_BASE + 0x64)
49-
5034
#define BLUE_LED_PIN 23
5135
#define RED_LED_PIN 24
5236

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