Added XMODEM update

Author: danielinux

hal/stm32h5.c

@@ -366,10 +366,23 @@ static void clock_pll_on(void)
 }
 
 #if (TZ_SECURE())
+
+#define NVIC_ISER_BASE (0xE000E100)
+#define NVIC_ICER_BASE (0xE000E180)
+#define NVIC_IPRI_BASE (0xE000E400)
+#define NVIC_USART3_IRQ 60
+
+/* Cortex M-33 has an extra register to set up non-secure interrupts */
+#define NVIC_ITNS_BASE (0xE000E380)
+
+
+
 static void periph_unsecure(void)
 {
     uint32_t pin;
     volatile uint32_t reg;
+    volatile uint32_t *nvic_itns;
+    uint32_t nvic_reg_pos, nvic_reg_off;
 
     /*Enable clock for User LED GPIOs */
     RCC_AHB2_CLOCK_ER|= LED_AHB2_ENABLE;
@@ -412,6 +425,13 @@ static void periph_unsecure(void)
         TZSC_SECCFGR1 = reg;
     }
 
+    /* Set USART3 interrupt as non-secure */
+    nvic_reg_pos = NVIC_USART3_IRQ / 32;
+    nvic_reg_off = NVIC_USART3_IRQ % 32;
+    nvic_itns = ((volatile uint32_t *)(NVIC_ITNS_BASE + 4 * nvic_reg_pos));
+    *nvic_itns |= (1 << nvic_reg_off);
+
+
     /* Disable GPIOs clock used previously for accessing SECCFGR registers */
 #if 0
     RCC_AHB2_CLOCK_ER &= ~GPIOA_AHB2_CLOCK_ER;

hal/stm32h5.h

@@ -23,7 +23,9 @@
 #ifndef STM32H5_DEF_INCLUDED
 #define STM32H5_DEF_INCLUDED
 /* Assembly helpers */
+#ifndef DMB
 #define DMB() __asm__ volatile ("dmb")
+#endif
 #define ISB() __asm__ volatile ("isb")
 #define DSB() __asm__ volatile ("dsb")
 
@@ -409,8 +411,14 @@
 #define UART_CR3_HDSEL          (1 << 3)
 #define UART_CR3_DEM            (1 << 14)
 #define UART_CR3_IREN           (1 << 1)
+#define UART_CR3_RXFTIE         (1 << 28)
 #define UART_ISR_TX_EMPTY       (1 << 7)
 #define UART_ISR_RX_NOTEMPTY    (1 << 5)
+#define UART_EPE                (1 << 0)    /* Parity error */
+#define UART_EFE                (1 << 1)    /* Framing error */
+#define UART_ENE                (1 << 2)    /* Noise error */
+#define UART_ORE                (1 << 3)    /* Overrun error */
+
 
 
 /* OTP FLASH AREA */

hal/uart/uart_drv_stm32h5.c

@@ -141,11 +141,18 @@ static int uart1_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
     return 0;
 }
 
+static void uart1_clear_errors(void)
+{
+    UART1_ICR = UART1_ISR & (UART_ENE | UART_EPE | UART_ORE | UART_EFE);
+}
+
 static int uart1_tx(const uint8_t c)
 {
     volatile uint32_t reg;
     do {
         reg = UART1_ISR;
+        if (reg & (UART_ENE | UART_EPE | UART_ORE | UART_EFE))
+            uart1_clear_errors();
     } while ((reg & UART_ISR_TX_EMPTY) == 0);
     UART1_TDR = c;
     return 1;
@@ -156,6 +163,8 @@ static int uart1_rx(uint8_t *c)
     volatile uint32_t reg;
     int i = 0;
     reg = UART1_ISR;
+    if (reg & (UART_ENE | UART_EPE | UART_ORE | UART_EFE))
+        uart1_clear_errors();
     if (reg & UART_ISR_RX_NOTEMPTY) {
         *c = (uint8_t)UART1_RDR;
         return 1;
@@ -209,11 +218,18 @@ static int uart3_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
     return 0;
 }
 
+static void uart3_clear_errors(void)
+{
+    UART3_ICR = UART3_ISR & (UART_ENE | UART_EPE | UART_ORE | UART_EFE);
+}
+
 static int uart3_tx(const uint8_t c)
 {
     volatile uint32_t reg;
     do {
         reg = UART3_ISR;
+        if (reg & (UART_ENE | UART_EPE | UART_ORE | UART_EFE))
+            uart3_clear_errors();
     } while ((reg & UART_ISR_TX_EMPTY) == 0);
     UART3_TDR = c;
     return 1;
@@ -224,6 +240,8 @@ static int uart3_rx(uint8_t *c)
     volatile uint32_t reg;
     int i = 0;
     reg = UART3_ISR;
+    if (reg & (UART_ENE | UART_EPE | UART_ORE | UART_EFE))
+        uart3_clear_errors();
     if (reg & UART_ISR_RX_NOTEMPTY) {
         *c = (uint8_t)UART3_RDR;
         return 1;