Add wolfBoot port for STM32U3 (NUCLEO-U385RG-Q)

New HAL port for the STM32U3 family (Cortex-M33, no TrustZone,
1MB dual-bank flash with 4KB pages, 64-bit double-word writes).

Features:
- hal/stm32u3.c, hal/stm32u3.h, hal/stm32u3.ld: flash driver,
  clock init (96 MHz MSIRC0 via EPOD booster), inline UART, ICACHE
- config/examples/stm32u3.config: ECC384/SHA384, DEBUG_UART=1,
  NVM_FLASH_WRITEONCE=1, RAM_CODE=1, dual-bank layout
- test-app/app_stm32u3.c: LED blink + UART output + version check
- tools/scripts/prepare_update_u3.sh: v2 pBOOT update image builder
- docs/Targets.md: STM32U3 section with build/flash/update instructions
- CI: stm32u3_test job + Clang rebuild coverage

Tested on NUCLEO-U385RG-Q:
- Verified boot with ECC384/SHA384 signature
- 96 MHz clock (MSIRC0 + SMPS + EPOD booster + VOS1)
- UART output on USART1 PA9/PA10 (ST-LINK VCP)
- TEST_FLASH erase/write/readback on both flash banks
- A/B firmware update (v1 -> v2 swap with pBOOT trigger)

Author: dgarske

.github/workflows/test-build.yml

@@ -50,6 +50,7 @@ jobs:
         if: |
           inputs.config-file == './config/examples/stm32h7.config' ||
           inputs.config-file == './config/examples/stm32h7-octospi.config' ||
+          inputs.config-file == './config/examples/stm32u3.config' ||
           inputs.config-file == './config/examples/stm32u5.config' ||
           inputs.config-file == './config/examples/stm32u5-wolfcrypt-tz.config' ||
           inputs.config-file == './config/examples/stm32u5-nonsecure-dualbank.config' ||

.github/workflows/test-configs.yml

@@ -536,6 +536,12 @@ jobs:
       arch: arm
       config-file: ./config/examples/stm32l5-wolfcrypt-tz.config
 
+  stm32u3_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/stm32u3.config
+
   stm32u5_nonsecure_dualbank_test:
     uses: ./.github/workflows/test-build.yml
     with:

arch.mk

@@ -255,6 +255,15 @@ ifeq ($(ARCH),ARM)
     SPI_TARGET=stm32
   endif
 
+  ifeq ($(TARGET),stm32u3)
+    CORTEX_M33=1
+    CFLAGS+=-Ihal
+    ARCH_FLASH_OFFSET=0x08000000
+    WOLFBOOT_ORIGIN=0x08000000
+    LSCRIPT_IN=hal/$(TARGET).ld
+    SPI_TARGET=stm32
+  endif
+
   ifeq ($(TARGET),stm32h5)
     CORTEX_M33=1
     CFLAGS+=-Ihal

config/examples/stm32u3.config

@@ -0,0 +1,32 @@
+ARCH?=ARM
+TZEN?=0
+TARGET?=stm32u3
+SIGN?=ECC384
+HASH?=SHA384
+DEBUG?=0
+VTOR?=1
+CORTEX_M0?=0
+CORTEX_M33?=1
+NO_ASM?=0
+NO_MPU=1
+EXT_FLASH?=0
+SPI_FLASH?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=1
+WOLFBOOT_VERSION?=1
+V?=0
+SPMATH?=1
+RAM_CODE?=1
+DUALBANK_SWAP?=0
+# Flash layout for dual-bank (2x512KB, 8KB pages):
+#   Bank 1 (0x08000000): wolfBoot (64KB) + BOOT partition (448KB)
+#   Bank 2 (0x08080000): UPDATE partition (448KB) + SWAP (8KB)
+# Future: DUALBANK_SWAP=1 eliminates swap and uses HW bank-swap
+WOLFBOOT_SECTOR_SIZE?=0x1000
+WOLFBOOT_PARTITION_SIZE?=0x70000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08010000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08080000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x080F0000
+FLAGS_HOME=0
+DISABLE_BACKUP=0
+DEBUG_UART=1

docs/Targets.md

@@ -1709,6 +1709,82 @@ arm-none-eabi-gdb
 ```
 
 
+## STM32U3
+
+The STM32U3 family (for example the STM32U385RG on NUCLEO-U385RG-Q) is a
+Cortex-M33 part **without TrustZone**, so the port is single-image only
+(no `-tz` or `-ns` variants). 1 MB internal flash, 256 KB SRAM, 8 KB
+pages, 128-bit (quad-word) flash write quantum.
+
+### Flash layout (stm32u3.config)
+
+Dual-bank flash (2 x 512 KB, 4 KB pages). Bank 1 holds wolfBoot + BOOT,
+bank 2 holds UPDATE + SWAP:
+
+```
+Bank 1:
+  0x08000000 - 0x0800FFFF  wolfBoot bootloader   (64 KB)
+  0x08010000 - 0x0807FFFF  BOOT partition        (0x70000, 448 KB)
+Bank 2:
+  0x08080000 - 0x080EFFFF  UPDATE partition      (0x70000, 448 KB)
+  0x080F0000 - 0x080F0FFF  SWAP sector           (4 KB)
+```
+
+### Clock and UART
+
+UART is always available in the test-app and enabled in wolfBoot via
+`DEBUG_UART=1` (on by default in the example config). USART1 on PA9
+(TX) / PA10 (RX), AF7, 115200 8N1 — the ST-LINK VCP on NUCLEO-U385RG-Q.
+
+### Building
+
+```sh
+cp config/examples/stm32u3.config .config
+make clean
+make
+```
+
+`DEBUG_UART=1` is enabled by default. To also run the flash self-test:
+
+```sh
+make TEST_FLASH=1
+```
+
+### Flashing
+
+Use `STM32_Programmer_CLI` (from STM32CubeIDE or STM32CubeProgrammer).
+`st-flash` does not yet support chipid 0x454.
+
+```sh
+STM32_Programmer_CLI -c port=SWD reset=HWrst -e all \
+    -d factory.bin 0x08000000 -v -rst
+```
+
+The test app blinks LD2 (PA5): slow on v1, fast on v2 (post-update).
+
+### Testing an Update
+
+Sign the test application as version 2 and write the update trigger
+magic (`pBOOT`) at the tail of the partition:
+
+```sh
+tools/keytools/sign --ecc384 --sha384 test-app/image.bin \
+    wolfboot_signing_private_key.der 2
+echo -n "pBOOT" > trigger_magic.bin
+./tools/bin-assemble/bin-assemble \
+  update.bin \
+    0x0     test-app/image_v2_signed.bin \
+    0x6FFFB trigger_magic.bin
+STM32_Programmer_CLI -c port=SWD reset=HWrst \
+    -d update.bin 0x08080000 -v -rst
+```
+
+Reset the board — wolfBoot verifies v2, swaps partitions, and jumps to
+the new image. LD2 transitions from the slow (v1) blink to the fast
+(v2) blink; with `DEBUG_UART=1` the UART log shows the v1 → v2
+transition.
+
+
 ## STM32H5
 
 Like [STM32L5](#stm32l5) and [STM32U5](#stm32u5), STM32H5 support is also demonstrated