|
| 1 | +/* kinetis.c |
| 2 | + * |
| 3 | + * Copyright (C) 2018 wolfSSL Inc. |
| 4 | + * |
| 5 | + * This file is part of wolfBoot. |
| 6 | + * |
| 7 | + * wolfBoot is free software; you can redistribute it and/or modify |
| 8 | + * it under the terms of the GNU General Public License as published by |
| 9 | + * the Free Software Foundation; either version 2 of the License, or |
| 10 | + * (at your option) any later version. |
| 11 | + * |
| 12 | + * wolfBoot is distributed in the hope that it will be useful, |
| 13 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | + * GNU General Public License for more details. |
| 16 | + * |
| 17 | + * You should have received a copy of the GNU General Public License |
| 18 | + * along with this program; if not, write to the Free Software |
| 19 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA |
| 20 | + */ |
| 21 | + |
| 22 | +#include <stdint.h> |
| 23 | +#include <target.h> |
| 24 | +#include "fsl_common.h" |
| 25 | +#include "fsl_flash.h" |
| 26 | +#include "fsl_ftfx_cache.h" |
| 27 | + |
| 28 | + |
| 29 | +#define CPU_CORE_CLOCK 120000000U |
| 30 | + |
| 31 | +static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) |
| 32 | +{ |
| 33 | + MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); |
| 34 | +} |
| 35 | + |
| 36 | +static flash_config_t pflash; |
| 37 | +static ftfx_cache_config_t pcache; |
| 38 | +static int flash_init = 0; |
| 39 | + |
| 40 | +/* This are the registers for the NV flash configuration area. |
| 41 | + * Access these field by setting the relative flags in NV_Flash_Config. |
| 42 | + */ |
| 43 | +#define NVTYPE_LEN (16) |
| 44 | + |
| 45 | +const uint8_t __attribute__((section(".flash_config"))) NV_Flash_Config[NVTYPE_LEN] = { |
| 46 | + /* Backdoor comparison key (2 words) */ |
| 47 | + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
| 48 | + |
| 49 | + /* P-Flash protection 1 */ |
| 50 | + 0xFF, 0xFF, |
| 51 | + /* P-Flash protection 2 */ |
| 52 | + 0xFF, 0xFF, |
| 53 | + |
| 54 | + /* Flash security register */ |
| 55 | + ((0xFE)), |
| 56 | + /* Flash option register */ |
| 57 | + 0xFF, |
| 58 | + /* EERAM protection register */ |
| 59 | + 0xFF, |
| 60 | + /* D-Flash protection register */ |
| 61 | + 0xFF |
| 62 | +}; |
| 63 | + |
| 64 | + |
| 65 | +/* Assert hook needed by Kinetis SDK */ |
| 66 | +void __assert_func(const char *a, int b, const char *c, const char *d) |
| 67 | +{ |
| 68 | + while(1) |
| 69 | + ; |
| 70 | +} |
| 71 | + |
| 72 | +#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ |
| 73 | +#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ |
| 74 | +#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */ |
| 75 | +#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ |
| 76 | +#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */ |
| 77 | +#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ |
| 78 | + |
| 79 | +static void CLOCK_CONFIG_FllStableDelay(void) |
| 80 | +{ |
| 81 | + uint32_t i = 30000U; |
| 82 | + while (i--) |
| 83 | + { |
| 84 | + __NOP(); |
| 85 | + } |
| 86 | +} |
| 87 | + |
| 88 | +/* Clock configuration for K64F */ |
| 89 | +const mcg_config_t mcgConfig_BOARD_BootClockRUN = |
| 90 | +{ |
| 91 | + .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ |
| 92 | + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */ |
| 93 | + .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ |
| 94 | + .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ |
| 95 | + .frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */ |
| 96 | + .drs = kMCG_DrsLow, /* Low frequency range */ |
| 97 | + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ |
| 98 | + .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */ |
| 99 | + .pll0Config = |
| 100 | + { |
| 101 | + .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ |
| 102 | + .prdiv = 0x13U, /* PLL Reference divider: divided by 20 */ |
| 103 | + .vdiv = 0x18U, /* VCO divider: multiplied by 48 */ |
| 104 | + }, |
| 105 | +}; |
| 106 | +const sim_clock_config_t simConfig_BOARD_BootClockRUN = |
| 107 | +{ |
| 108 | + .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ |
| 109 | + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ |
| 110 | + .clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */ |
| 111 | +}; |
| 112 | +const osc_config_t oscConfig_BOARD_BootClockRUN = |
| 113 | +{ |
| 114 | + .freq = 50000000U, /* Oscillator frequency: 50000000Hz */ |
| 115 | + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ |
| 116 | + .workMode = kOSC_ModeExt, /* Use external clock */ |
| 117 | + .oscerConfig = |
| 118 | + { |
| 119 | + .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ |
| 120 | + } |
| 121 | +}; |
| 122 | + |
| 123 | +static void do_flash_init(void) |
| 124 | +{ |
| 125 | + if (flash_init) |
| 126 | + return; |
| 127 | + flash_init++; |
| 128 | + memset(&pflash, 0, sizeof(pflash)); |
| 129 | + memset(&pcache, 0, sizeof(pcache)); |
| 130 | + FLASH_Init(&pflash); |
| 131 | + FTFx_CACHE_Init(&pcache); |
| 132 | + FTFx_CACHE_ClearCachePrefetchSpeculation(&pcache, 1); |
| 133 | +} |
| 134 | + |
| 135 | +int hal_flash_write(uint32_t address, const uint8_t *data, int len) |
| 136 | +{ |
| 137 | + int w = 0; |
| 138 | + int ret; |
| 139 | + do_flash_init(); |
| 140 | + |
| 141 | + while (len > 0) { |
| 142 | + if ((len < 8) || address & 0x07) { |
| 143 | + uint8_t aligned_dword[8]; |
| 144 | + uint32_t address_align = address - (address & 0x07); |
| 145 | + uint32_t start_off = address - address_align; |
| 146 | + int i; |
| 147 | + memcpy(aligned_dword, address_align, 8); |
| 148 | + for (i = start_off; ((i < 8) && (i < len + start_off)); i++) |
| 149 | + aligned_dword[i] = data[w++]; |
| 150 | + ret = FLASH_Program(&pflash, address_align, aligned_dword, 8); |
| 151 | + if (ret != kStatus_FTFx_Success) |
| 152 | + return -1; |
| 153 | + address += i; |
| 154 | + len -= i; |
| 155 | + } else { |
| 156 | + uint32_t len_align = len - (len & 0x07); |
| 157 | + ret = FLASH_Program(&pflash, address, data + w, len_align); |
| 158 | + if (ret != kStatus_FTFx_Success) |
| 159 | + return -1; |
| 160 | + len -= len_align; |
| 161 | + address += len_align; |
| 162 | + } |
| 163 | + } |
| 164 | + return 0; |
| 165 | +} |
| 166 | + |
| 167 | +void hal_flash_unlock(void) |
| 168 | +{ |
| 169 | +} |
| 170 | + |
| 171 | +void hal_flash_lock(void) |
| 172 | +{ |
| 173 | +} |
| 174 | + |
| 175 | + |
| 176 | +int hal_flash_erase(uint32_t address, int len) |
| 177 | +{ |
| 178 | + int idx = 0; |
| 179 | + do_flash_init(); |
| 180 | + do { |
| 181 | + if (FLASH_Erase(&pflash, address + WOLFBOOT_SECTOR_SIZE * idx, WOLFBOOT_SECTOR_SIZE, kFTFx_ApiEraseKey) != kStatus_FTFx_Success) |
| 182 | + return -1; |
| 183 | + len -= WOLFBOOT_SECTOR_SIZE; |
| 184 | + idx++; |
| 185 | + } while (len > 0); |
| 186 | + return 0; |
| 187 | +} |
| 188 | + |
| 189 | +void hal_init(void) |
| 190 | +{ |
| 191 | + /* Set the system clock dividers in SIM to safe value. */ |
| 192 | + CLOCK_SetSimSafeDivs(); |
| 193 | + /* Initializes OSC0 according to board configuration. */ |
| 194 | + CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN); |
| 195 | + CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq); |
| 196 | + /* Configure the Internal Reference clock (MCGIRCLK). */ |
| 197 | + CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, |
| 198 | + mcgConfig_BOARD_BootClockRUN.ircs, |
| 199 | + mcgConfig_BOARD_BootClockRUN.fcrdiv); |
| 200 | + /* Configure FLL external reference divider (FRDIV). */ |
| 201 | + CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv); |
| 202 | + /* Set MCG to PEE mode. */ |
| 203 | + CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, |
| 204 | + kMCG_PllClkSelPll0, |
| 205 | + &mcgConfig_BOARD_BootClockRUN.pll0Config); |
| 206 | + /* Set the clock configuration in SIM module. */ |
| 207 | + CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN); |
| 208 | + do_flash_init(); |
| 209 | +} |
| 210 | + |
| 211 | +void hal_prepare_boot(void) |
| 212 | +{ |
| 213 | +} |
| 214 | + |
| 215 | + |
0 commit comments