Skip to content

Commit 7b1d180

Browse files
dgarskedanielinux
dgarske
authored and
danielinux
committed
Improvements for CPLD. Patch for PCIe from TigerLake.
1 parent ffa31ca commit 7b1d180

3 files changed

Lines changed: 93 additions & 36 deletions

File tree

‎hal/nxp_t1024.c‎

Lines changed: 69 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -104,9 +104,14 @@ static void hal_flash_unlock_sector(uint32_t sector);
104104
#define DCFG_DEVDISR4 ((volatile uint32_t*)(DCFG_BASE + 0x7CUL)) /* Device disable register */
105105
#define DCFG_DEVDISR5 ((volatile uint32_t*)(DCFG_BASE + 0x80UL)) /* Device disable register */
106106
#define DCFG_COREDISR ((volatile uint32_t*)(DCFG_BASE + 0x94UL)) /* Core Enable/Disable */
107+
#define DCFG_RCWSR(n) ((volatile uint32_t*)(DCFG_BASE + 0x100UL + ((n) * 4))) /* Reset Control Word Status Register (0-15) */
107108
#define DCFG_BRR ((volatile uint32_t*)(DCFG_BASE + 0xE4UL)) /* Boot Release Register (DCFG_CCSR_BRR) */
108109
#define DCFG_DCSR ((volatile uint32_t*)(DCFG_BASE + 0x704UL)) /* Debug configuration and status */
109110

111+
/* RCW */
112+
#define RCWSR4_SRDS1_PRTCL 0xFF800000
113+
#define RCWSR4_SRDS1_PRTCL_SHIFT 23
114+
110115
/* Logical I/O Device Number */
111116
#define DCFG_USB1LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x520))
112117
#define DCFG_USB2LIODNR ((volatile uint32_t*)(DCFG_BASE + 0x524))
@@ -666,13 +671,12 @@ enum ifc_amask_sizes {
666671
#define POWER_STATUS_ADDRR 0x0400
667672
#define MPU_INT_STATUS_ADDR 0x0402
668673
#define MPU_INT_ENABLE_ADDR 0x0404
669-
#define MPU_CONTROL_ADDR 0x042E
670-
#define MPU_RESET_ADDR 0x0430
671-
#define PCI_STATUS_ADDR 0x0432
672-
#define HS_CSR_ADDR 0x103C
673-
#define CPCI_GA_ADDRS 0x103E
674-
#define CPCI_INTX_ADDR 0x1040
675-
#define PLD_CURRENT_VERSION 0x1042
674+
#define MPU_CONTROL_ADDR 0x0430
675+
#define MPU_RESET_ADDR 0x0432
676+
#define PCI_STATUS_ADDR 0x0434
677+
#define HS_CSR_ADDR 0x1040
678+
#define CPCI_GA_ADDRS 0x1042
679+
#define CPCI_INTX_ADDR 0x1044
676680

677681
#define CPLD_LBMAP_MASK 0x3F
678682
#define CPLD_BANK_SEL_MASK 0x07
@@ -687,7 +691,9 @@ enum ifc_amask_sizes {
687691
#define CPLD_OVERRIDE_BOOT_EN 0x01
688692
#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */
689693

690-
#define CPLD_DATA(n) ((volatile uint16_t*)(CPLD_BASE + n))
694+
#define CPLD_DATA(n) ((volatile uint16_t*)(CPLD_BASE + (n)))
695+
#define CPLD_READ(reg) get16(CPLD_DATA(((reg))))
696+
#define CPLD_WRITE(reg, value) set16(CPLD_DATA((reg), (value)))
691697

692698

693699
/* eSPI */
@@ -1193,9 +1199,11 @@ static int pcie_bus = 0;
11931199
void io_write32(uint16_t port, uint32_t value)
11941200
{
11951201
if (port == PCI_CONFIG_ADDR_PORT) {
1202+
//wolfBoot_printf("WRITE32 Addr %x\n", value);
11961203
set32(PCIE_CONFIG_ADDR(pcie_bus), value);
11971204
}
11981205
else if (port == PCI_CONFIG_DATA_PORT) {
1206+
//wolfBoot_printf("WRITE32 Data %x\n", value);
11991207
#ifdef BIG_ENDIAN_ORDER
12001208
value = __builtin_bswap32(value);
12011209
#endif
@@ -1207,12 +1215,14 @@ uint32_t io_read32(uint16_t port)
12071215
uint32_t value = 0;
12081216
if (port == PCI_CONFIG_ADDR_PORT) {
12091217
value = get32(PCIE_CONFIG_ADDR(pcie_bus));
1218+
//wolfBoot_printf("READ32 Addr %x\n", value);
12101219
}
12111220
else if (port == PCI_CONFIG_DATA_PORT) {
12121221
value = get32(PCIE_CONFIG_DATA(pcie_bus));
12131222
#ifdef BIG_ENDIAN_ORDER
12141223
value = __builtin_bswap32(value);
12151224
#endif
1225+
//wolfBoot_printf("READ32 Data %x\n", value);
12161226
}
12171227
return value;
12181228
}
@@ -1253,6 +1263,27 @@ static int hal_pcie_init(void)
12531263
uint64_t mem_phys_h, io_phys_h;
12541264
uint32_t mem_phys, io_phys;
12551265
uint32_t mem_virt, io_virt;
1266+
uint32_t rcw4, srds_prtcl_s1;
1267+
uint16_t cpld_pci;
1268+
1269+
/* Configure Lane B */
1270+
cpld_pci = CPLD_READ(PCI_STATUS_ADDR);
1271+
rcw4 = get32(DCFG_RCWSR(4));
1272+
srds_prtcl_s1 = (rcw4 & RCWSR4_SRDS1_PRTCL) >> RCWSR4_SRDS1_PRTCL_SHIFT;
1273+
wolfBoot_printf("CPLD PCI 0x%x, RCW4 0x%x, SRDS1_PRTCL 0x%x\n",
1274+
cpld_pci, rcw4, srds_prtcl_s1);
1275+
if (srds_prtcl_s1 == 0x95) {
1276+
/* Route Lane B to PCIE */
1277+
set16(CPLD_DATA(PCI_STATUS_ADDR), cpld_pci & ~CPLD_PCIE_SGMII_MUX);
1278+
wolfBoot_printf("Route Lane B->PCIE\n");
1279+
}
1280+
else {
1281+
/* Route Lane B to SGMII */
1282+
set16(CPLD_DATA(PCI_STATUS_ADDR), cpld_pci | CPLD_PCIE_SGMII_MUX);
1283+
wolfBoot_printf("Route Lane B->SGMII\n");
1284+
}
1285+
cpld_pci = CPLD_READ(PCI_STATUS_ADDR);
1286+
wolfBoot_printf("CPLD PCI 0x%x\n", cpld_pci);
12561287

12571288
for (pcie_bus=1; pcie_bus<=PCIE_MAX_CONTROLLERS; pcie_bus++) {
12581289
/* Check device disable register */
@@ -1411,12 +1442,32 @@ static void hal_cpld_ifc_init(uint32_t base, uint32_t base_high, uint8_t ifc)
14111442
set32(IFC_CSOR(ifc), 0);
14121443
}
14131444
#endif
1445+
1446+
#if defined(ENABLE_CPLD) && defined(DEBUG)
1447+
void hal_cpld_dump(void)
1448+
{
1449+
wolfBoot_printf("\n--------------------\n");
1450+
wolfBoot_printf("CPLD Dump\n");
1451+
wolfBoot_printf("BOARD_ID_L_Addr = 0x%04x\n", CPLD_READ(BOARD_ID_L_ADDR));
1452+
wolfBoot_printf("BOARD_ID_H_Addr = 0x%04x\n", CPLD_READ(BOARD_ID_H_ADDR));
1453+
wolfBoot_printf("PLD_VER_Addr = 0x%04x\n", CPLD_READ(PLD_VER_ADDR));
1454+
wolfBoot_printf("Power_Status_Addrr = 0x%04x\n", CPLD_READ(POWER_STATUS_ADDRR));
1455+
wolfBoot_printf("MPU_Int_Status_Addr = 0x%04x\n", CPLD_READ(MPU_INT_STATUS_ADDR));
1456+
wolfBoot_printf("MPU_Int_Enable_Addr = 0x%04x\n", CPLD_READ(MPU_INT_ENABLE_ADDR));
1457+
wolfBoot_printf("MPU_Control_Addr = 0x%04x\n", CPLD_READ(MPU_CONTROL_ADDR));
1458+
wolfBoot_printf("MPU_Reset_Addr = 0x%04x\n", CPLD_READ(MPU_RESET_ADDR));
1459+
wolfBoot_printf("PCI_Status_Addr = 0x%04x\n", CPLD_READ(PCI_STATUS_ADDR));
1460+
wolfBoot_printf("HS_CSR_Addr = 0x%04x\n", CPLD_READ(HS_CSR_ADDR));
1461+
wolfBoot_printf("CPCI_GA_Addr = 0x%04x\n", CPLD_READ(CPCI_GA_ADDRS));
1462+
wolfBoot_printf("CPCI_INTx_Addr = 0x%04x\n", CPLD_READ(CPCI_INTX_ADDR));
1463+
wolfBoot_printf("\n--------------------\n");
1464+
}
1465+
#endif
1466+
14141467
static void hal_cpld_init(void)
14151468
{
14161469
#ifdef ENABLE_CPLD
1417-
#ifdef DEBUG
1418-
uint32_t fw;
1419-
#endif
1470+
uint32_t reg;
14201471

14211472
/* CPLD (APU) IFC 2 - LAW 2, TLB 1.11 */
14221473
hal_cpld_ifc_init(CPLD_BASE, CPLD_BASE_PHYS_HIGH, 2);
@@ -1435,12 +1486,14 @@ static void hal_cpld_init(void)
14351486
(MAS3_SX | MAS3_SW | MAS3_SR),
14361487
(MAS2_I | MAS2_G), 0, BOOKE_PAGESZ_256K, 1);
14371488

1489+
reg = CPLD_READ(BOARD_ID_L_ADDR) << 16;
1490+
reg |= CPLD_READ(BOARD_ID_H_ADDR);
1491+
wolfBoot_printf("CPLD BOARD_ID: 0x%x\n", reg);
1492+
reg = CPLD_READ(PLD_VER_ADDR);
1493+
wolfBoot_printf("CPLD PLD_VER: 0x%x\n", reg);
1494+
14381495
#ifdef DEBUG
1439-
fw = get16(CPLD_DATA(BOARD_ID_L_ADDR)) << 16;
1440-
fw |= get16(CPLD_DATA(BOARD_ID_H_ADDR));
1441-
wolfBoot_printf("CPLD BOARD_ID: 0x%x\n", fw);
1442-
fw = get16(CPLD_DATA(PLD_VER_ADDR));
1443-
wolfBoot_printf("CPLD PLD_VER: 0x%x\n", fw);
1496+
hal_cpld_dump();
14441497
#endif
14451498
#endif /* ENABLE_CPLD */
14461499
}

‎hal/nxp_t2080.c‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -105,23 +105,23 @@
105105

106106
/* IFC AMASK - RM Table 13-3 - Count of MSB minus 1 */
107107
enum ifc_amask_sizes {
108-
IFC_AMASK_64KB = 0xFFFF,
109-
IFC_AMASK_128KB = 0xFFFE,
110-
IFC_AMASK_256KB = 0xFFFC,
111-
IFC_AMASK_512KB = 0xFFF8,
112-
IFC_AMASK_1MB = 0xFFF0,
113-
IFC_AMASK_2MB = 0xFFE0,
114-
IFC_AMASK_4MB = 0xFFC0,
115-
IFC_AMASK_8MB = 0xFF80,
116-
IFC_AMASK_16MB = 0xFF00,
117-
IFC_AMASK_32MB = 0xFE00,
118-
IFC_AMASK_64MB = 0xFC00,
119-
IFC_AMASK_128MB = 0xF800,
120-
IFC_AMASK_256MB = 0xF000,
121-
IFC_AMASK_512MB = 0xE000,
122-
IFC_AMASK_1GB = 0xC000,
123-
IFC_AMASK_2GB = 0x8000,
124-
IFC_AMASK_4GB = 0x0000,
108+
IFC_AMASK_64KB = 0xFFFF0000,
109+
IFC_AMASK_128KB = 0xFFFE0000,
110+
IFC_AMASK_256KB = 0xFFFC0000,
111+
IFC_AMASK_512KB = 0xFFF80000,
112+
IFC_AMASK_1MB = 0xFFF00000,
113+
IFC_AMASK_2MB = 0xFFE00000,
114+
IFC_AMASK_4MB = 0xFFC00000,
115+
IFC_AMASK_8MB = 0xFF800000,
116+
IFC_AMASK_16MB = 0xFF000000,
117+
IFC_AMASK_32MB = 0xFE000000,
118+
IFC_AMASK_64MB = 0xFC000000,
119+
IFC_AMASK_128MB = 0xF8000000,
120+
IFC_AMASK_256MB = 0xF0000000,
121+
IFC_AMASK_512MB = 0xE0000000,
122+
IFC_AMASK_1GB = 0xC0000000,
123+
IFC_AMASK_2GB = 0x80000000,
124+
IFC_AMASK_4GB = 0x00000000,
125125
};
126126

127127

‎src/pci.c‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,14 +50,18 @@
5050
#define PCI_DATA_HI16_MASK (0xffff0000)
5151
#define PCI_DATA_HI16_SHIFT (16)
5252

53+
/* PCI address space starts at 0x80000000 (2GB), on TGL ECAM starts at
54+
* 0xC0000000 (3GB). So there is 1 GB under the 4GB boundary available. By
55+
* default allocate 128MB for normal memory and 896MB for prefetchable
56+
* memory. */
5357
#ifndef PCI_MMIO32_BASE
5458
#define PCI_MMIO32_BASE 0x80000000ULL
55-
#define PCI_MMIO32_LENGTH (1024U * 1024U * 1024U)
59+
#define PCI_MMIO32_LENGTH (128U * 1024U * 1024U)
5660
#endif /* PCI_MMIO32_BASE */
5761

5862
#ifndef PCI_MMIO32_PREFETCH_BASE
59-
#define PCI_MMIO32_PREFETCH_BASE (PCI_MMIO32_BASE + (1024ULL * 1024ULL * 1024ULL))
60-
#define PCI_MMIO32_PREFETCH_LENGTH (1024UL * 1024U * 1024U)
63+
#define PCI_MMIO32_PREFETCH_BASE (PCI_MMIO32_BASE + PCI_MMIO32_LENGTH)
64+
#define PCI_MMIO32_PREFETCH_LENGTH (896U * 1024U * 1024U)
6165
#endif /* PCI_MMIO32_PREFETCH_BASE */
6266

6367
#ifndef PCI_IO32_BASE

0 commit comments

Comments
 (0)