2121
2222#include <stdint.h>
2323#include <target.h>
24+ #include <string.h>
2425#include "image.h"
2526
2627#include "cy_device_headers.h"
3132#include "cy_syslib.h"
3233#include "cy_ipc_drv.h"
3334
34- #define ROW_SIZE (0x200)
35+ #define ROW_SIZE (0x1000)
36+ #define FLASH_BASE_ADDRESS (0x10000000)
3537#define CPU_FREQ (100000000)
3638
39+ uint8_t psoc6_write_buffer [ROW_SIZE ];
40+
3741#ifndef NVM_FLASH_WRITEONCE
3842# error "wolfBoot psoc6 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
3943#endif
@@ -67,10 +71,9 @@ static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
6771 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO ,
6872};
6973
70- void hal_init (void )
74+ #define MPU_CTL *((volatile uint32_t *)(0xE000ED90))
75+ static void hal_set_pll (void )
7176{
72- SystemInit ();
73- #if 0
7477 /*Set clock path 1 source to IMO, this feeds PLL1*/
7578 Cy_SysClk_ClkPathSetSource (1U , CY_SYSCLK_CLKPATH_IN_IMO );
7679
@@ -97,8 +100,15 @@ void hal_init(void)
97100 while (1 )
98101 ;
99102 }
100- #endif
103+ }
104+
105+ void hal_init (void )
106+ {
107+ MPU_CTL = 0 ;
108+ //SystemInit();
109+ Cy_PDL_Init (CY_DEVICE_CFG );
101110 Cy_Flash_Init ();
111+ //hal_set_pll();
102112}
103113
104114void hal_prepare_boot (void )
@@ -114,10 +124,18 @@ void hal_prepare_boot(void)
114124 */
115125int RAMFUNCTION hal_flash_write (uint32_t address , const uint8_t * data , int len )
116126{
127+ const uint8_t * src = data ;
117128 if (len < NVM_CACHE_SIZE )
118129 return -1 ;
130+ if ((((uint32_t )data ) & FLASH_BASE_ADDRESS ) == FLASH_BASE_ADDRESS ) {
131+ if (len != ROW_SIZE ) {
132+ return -1 ;
133+ }
134+ memcpy (psoc6_write_buffer , data , len );
135+ src = psoc6_write_buffer ;
136+ }
119137 while (len ) {
120- Cy_Flash_WriteRow (address , (const uint32_t * ) data );
138+ Cy_Flash_ProgramRow (address , (const uint32_t * ) src );
121139 len -= NVM_CACHE_SIZE ;
122140 if ((len > 0 ) && (len < NVM_CACHE_SIZE ))
123141 return -1 ;
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