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dgarskedanielinux
dgarske
authored and
danielinux
committed
Fixes for regression testing on NXP T2080. Fix legacy U-Boot image header load address (make optional feature). Cleanup disabled/dead code.
1 parent db15f9b commit 63766c2

7 files changed

Lines changed: 146 additions & 100 deletions

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‎arch.mk‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -339,6 +339,11 @@ ifeq ($(TARGET),nxp_p1021)
339339
SPI_TARGET=nxp
340340
endif
341341

342+
ifeq ($(TARGET),zynq)
343+
# Support detection and skip of U-Boot legecy header */
344+
CFLAGS+=-DWOLFBOOT_UBOOT_LEGACY
345+
endif
346+
342347
ifeq ($(TARGET),ti_hercules)
343348
# HALCoGen Source and Include?
344349
CORTEX_R5=1

‎hal/nxp_p1021.c‎

Lines changed: 24 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@
3636
#define ENABLE_ESPI /* SPI for TPM */
3737
#define ENABLE_MP /* multi-core support */
3838
#define ENABLE_IRQ
39-
40-
/* TODO - Ethernet*/
39+
/* #define ENABLE_QE_CRC32 */ /* CRC32 check on QE disabled by default */
40+
/* #define ENABLE_ETHERNET */ /* Does not support Ethernet UEC */
4141
#endif
4242

4343
/* Debugging */
@@ -93,6 +93,17 @@ static int test_tpm(void);
9393
#define GUTS_DEVDISR_TB1 0x00001000
9494

9595

96+
/* L2 Cache */
97+
#define L2_BASE (CCSRBAR + 0x20000)
98+
#define L2CTL (volatile uint32_t*)(L2_BASE + 0x000) /* 0xFFE20000 - L2 control register */
99+
#define L2SRBAR0 (volatile uint32_t*)(L2_BASE + 0x100) /* 0xFFE20100 - L2 SRAM base address register */
100+
101+
#define L2CTL_EN (1 << 31) /* L2 enable */
102+
#define L2CTL_INV (1 << 30) /* L2 invalidate */
103+
#define L2CTL_SIZ(n) (((n) & 0x3) << 28) /* 2=256KB (always) */
104+
#define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */
105+
106+
96107
/* PIC */
97108
#define PIC_BASE (CCSRBAR + 0x40000)
98109
#define PIC_WHOAMI ((volatile uint32_t*)(PIC_BASE + 0x0090UL)) /* Returns the ID of the processor core reading this register */
@@ -1018,7 +1029,7 @@ static int hal_cpld_init(void)
10181029
ELBC_ORG_CSCT | ELBC_ORG_XACS | ELBC_ORG_SCY | ELBC_ORG_TRLX |
10191030
ELBC_ORG_EHTR | ELBC_ORG_EAD));
10201031

1021-
#if 0 /* ethernet (uec) setup not required */
1032+
#ifdef ENABLE_ETHERNET /* ethernet (uec) setup not required */
10221033
/* reset micrel phy for each UEC */
10231034
set8(BCSR11, get8(BCSR11) & ~BCSR11_ENET_MICRST);
10241035
set8(BCSR11, get8(BCSR11) | BCSR11_ENET_MICRST);
@@ -1267,7 +1278,7 @@ static void qe_upload_microcode(const struct qe_firmware *firmware,
12671278
}
12681279

12691280
/* Upload a microcode to the I-RAM at a specific address */
1270-
int qe_upload_firmware(const struct qe_firmware *firmware)
1281+
static int qe_upload_firmware(const struct qe_firmware *firmware)
12711282
{
12721283
unsigned int i, j;
12731284
uint32_t crc;
@@ -1312,7 +1323,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
13121323
return -1;
13131324
}
13141325

1315-
#if 0 /* Disabled for wolfBoot */
1326+
#ifdef ENABLE_QE_CRC32
13161327
/* Validate the CRC */
13171328
crc = *(uint32_t *)((void *)firmware + calc_size);
13181329
if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
@@ -1495,6 +1506,9 @@ static void hal_mp_init(void)
14951506
uint32_t *fixup = (uint32_t*)&_mp_page_start;
14961507
uint32_t bootpg;
14971508
int i_tlb = 0; /* always 0 */
1509+
size_t i;
1510+
const uint32_t *s;
1511+
uint32_t *d;
14981512

14991513
/* Assign virtual boot page at end of DDR */
15001514
bootpg = DDR_ADDRESS + DDR_SIZE - BOOT_ROM_SIZE;
@@ -1509,18 +1523,12 @@ static void hal_mp_init(void)
15091523
0, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
15101524

15111525
/* copy startup code to virtually mapped boot address */
1512-
#if 0 /* not use memcpy due to compiler array bounds report (not valid) */
1513-
memcpy((void*)BOOT_ROM_ADDR, fixup, BOOT_ROM_SIZE);
1514-
#else
1515-
{
1516-
size_t i;
1517-
const uint32_t *s = (const uint32_t*)fixup;
1518-
uint32_t *d = (uint32_t*)BOOT_ROM_ADDR;
1519-
for (i = 0; i < BOOT_ROM_SIZE/4; i++) {
1520-
d[i] = s[i];
1521-
}
1526+
/* do not use memcpy due to compiler array bounds report (not valid) */
1527+
s = (const uint32_t*)fixup;
1528+
d = (uint32_t*)BOOT_ROM_ADDR;
1529+
for (i = 0; i < BOOT_ROM_SIZE/4; i++) {
1530+
d[i] = s[i];
15221531
}
1523-
#endif
15241532

15251533
/* start core and wait for it to be enabled */
15261534
hal_mp_up(bootpg);
@@ -1538,11 +1546,6 @@ void hal_irq_init(void)
15381546

15391547
set32(PIC_GCR, PIC_GCR_M); /* eanble mixed-mode */
15401548
reg = get32(PIC_GCR); /* read back */
1541-
1542-
#if 0 /* interrupt function not setup */
1543-
/* Decrement interrupt enable */
1544-
mtspr(SPRN_TCR, TCR_DIE);
1545-
#endif
15461549
}
15471550
#endif
15481551

‎hal/nxp_ppc.h‎

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,9 @@
6363
#define MMU_V2
6464
#define ENABLE_L1_CACHE
6565
#define ENABLE_L2_CACHE
66-
#define L2SRAM_ADDR (0xFEC20000) /* Setup L2 as SRAM */
66+
#define L2SRAM_ADDR (0xFEC20000) /* L2 as SRAM */
67+
#define L2SRAM_SIZE (256 * 1024)
68+
#define ENABLE_INTERRUPTS
6769

6870
#define ENABLE_DDR
6971

@@ -154,6 +156,8 @@
154156

155157
#ifndef L1_CACHE_LINE_SIZE
156158
#define L1_CACHE_LINE_SIZE (1 << L1_CACHE_LINE_SHIFT)
159+
160+
#define CPC_BASE (CCSRBAR + 0x10000)
157161
#endif
158162

159163

@@ -318,18 +322,6 @@
318322
})
319323
#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
320324

321-
322-
/* L2 Cache */
323-
#define L2_BASE (CCSRBAR + 0x20000)
324-
#define L2CTL (volatile uint32_t*)(L2_BASE + 0x000) /* 0xFFE20000 - L2 control register */
325-
#define L2SRBAR0 (volatile uint32_t*)(L2_BASE + 0x100) /* 0xFFE20100 - L2 SRAM base address register */
326-
327-
#define L2CTL_EN (1 << 31) /* L2 enable */
328-
#define L2CTL_INV (1 << 30) /* L2 invalidate */
329-
#define L2CTL_SIZ(n) (((n) & 0x3) << 28) /* 2=256KB (always) */
330-
#define L2CTL_L2SRAM(n) (((n) & 0x7) << 16) /* 1=all 256KB, 2=128KB */
331-
332-
333325
#ifndef __ASSEMBLER__
334326

335327
/* The data barrier / coherency safe functions for reading and writing */

‎hal/nxp_t2080.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,7 @@
6969
enum law_target_id {
7070
LAW_TRGT_DDR_1 = 0x10,
7171
LAW_TRGT_BMAN = 0x18, /* Buffer Manager (BMan) (control) */
72+
LAW_TRGT_CORENET = 0x1E,
7273
LAW_TRGT_IFC = 0x1F, /* Integrated Flash Controller */
7374
};
7475

@@ -105,7 +106,6 @@ enum law_sizes {
105106
LAW_SIZE_1TB,
106107
};
107108

108-
109109
/* T2080 IFC (Integrated Flash Controller) - RM 13.3 */
110110
#define IFC_BASE (CCSRBAR + 0x00124000)
111111
#define IFC_MAX_BANKS 8

‎hal/nxp_t2080.ld‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ MEMORY
1313
{
1414
FLASH (rx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @BOOTLOADER_PARTITION_SIZE@
1515

16-
/* L1 - 16KB */
17-
RAM (rwx) : ORIGIN = 0xFDD00000, LENGTH = 0x4000
16+
/* L2 as SRAM - 256KB */
17+
RAM (rwx) : ORIGIN = 0xFEC20000, LENGTH = 0x40000
1818

1919
/* DDR - 2GB */
2020
DRAM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x7FFFFFFF

‎src/boot_ppc_start.S‎

Lines changed: 106 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,9 @@ reset_exceptions:
144144
mttbl r0 /* prevent FIT and WDT exceptions */
145145
mttbu r0
146146
mtspr SPRN_TSR, r1 /* clear all timer exception status */
147+
#ifdef PLATFORM_nxp_p1021
147148
mtspr SPRN_TCR, r0 /* disable all timers */
149+
#endif
148150
mtspr SPRN_ESR, r0 /* clear exception syndrome register */
149151
mtspr SPRN_MCSR, r0 /* clear machine check syndrome register */
150152
mtxer r0 /* clear integer exception register */
@@ -155,7 +157,7 @@ hardware_reg:
155157
ori r0, r0, (HID0_EMCP | HID0_TBEN | HID0_ENMAS7)@l
156158
mtspr SPRN_HID0, r0
157159

158-
#ifndef BUILD_LOADER_STAGE1
160+
#if defined(PLATFORM_nxp_p1021) && !defined(BUILD_LOADER_STAGE1)
159161
/* Set addr streaming & broadcast
160162
* and optimized sync instruction (if rev 5.0 or greater) */
161163
li r0, (HID1_ASTME | HID1_ABE)@l
@@ -223,6 +225,7 @@ find_pc:
223225
andc r2, r2, r3
224226
or r2, r2, r1
225227
mtspr MAS2, r2 /* EPN */
228+
226229
mfspr r2, MAS3
227230
andc r2, r2, r3
228231
or r2, r2, r1
@@ -242,7 +245,7 @@ find_pc:
242245
li r3, 0
243246
mtspr MAS1, r3
244247
1: cmpw r3, r14
245-
rlwinm r5, r5, 16, MAS0_ESEL_MSK
248+
rlwinm r5, r3, 16, MAS0_ESEL_MSK
246249
addi r3, r3, 1
247250
beq 2f /* skip the TLB in R14 */
248251

@@ -397,78 +400,118 @@ flash_tlb:
397400
BOOKE_PAGESZ_256M, 0, r3);
398401
#endif
399402

400-
#ifdef ENABLE_L2_CACHE
401-
402-
#ifdef MMU_V2
403+
#if defined(ENABLE_L2_CACHE) && defined(MMU_V2)
403404

404-
/* e6500 - must have L2 initialized before L1 */
405-
/* E6500RM 5.6.2 Enabling and disabling the L1 caches:
406-
* "Note that enabling either L1 cache without first enabling the L2 cache
407-
* is not supported."
408-
*/
409405
create_ccsr_l2_tlb:
410-
/* L2 0xFEC20000: TLB 1, Entry 9, Supervisor X/R/W, G, TS=0, 256KB, IPROT */
406+
/* L2 0xFEC20000: TLB 1, Entry 9, Supervisor X/R/W, IG, TS=0, 512KB, IPROT */
411407
set_tlb(1, 9,
412408
L2SRAM_ADDR, L2SRAM_ADDR, 0,
413-
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G, 0,
414-
BOOKE_PAGESZ_256K, 1, r3);
415-
416-
/* CRM 11.7 */
417-
setup_l2:
418-
419-
/* L2 data cache invalidation & unlocking
420-
* create flash invalidate & unlock bit mask (see Table 2-19)
421-
*/
422-
lis r4, 0x0020
423-
ori r4, r4, 0x0400
424-
/* get base address of memory mapped registers */
425-
mfspr r5, SCCSRBAR
426-
li r7, 24 /* get shift count */
427-
sld r5, r5, r7
428-
lis r6, 0x00C2 /* block offset for desired cluster (see Table 2-4) */
429-
/* subsequent cluster L2 caches may be invalidated & unlocked by adding 0x40000 to 6 */
430-
add r6, r6, r5
431-
/* L2SC0 offset (see Table 2-5), included here only for example */
432-
/*addi r6, r6, r0 */
433-
/* ensure prior memory transactions are performed */
409+
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0,
410+
BOOKE_PAGESZ_512K, 1, r3);
411+
412+
setup_l2_sram:
413+
/* 8.2 CoreNet Platform Cache (CPC) Memory Map */
414+
#define CPCCSR0 (0x000)
415+
#define CPCSRCR1 (0x100)
416+
#define CPCSRCR0 (0x104)
417+
#define CPCHDBCR0 (0xF00)
418+
419+
#define CPCCSR0_CPCE (0x80000000 >> 0)
420+
#define CPCCSR0_CPCPE (0x80000000 >> 1)
421+
#define CPCCSR0_CPCFI (0x80000000 >> 10)
422+
#define CPCCSR0_CPCLFC (0x80000000 >> 21)
423+
#define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE)
424+
425+
#define CPCSRCR0_SRAMSZ_64 (0x1 << 1) /* ways 14-15 */
426+
#define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */
427+
#define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */
428+
#define CPCSRCR0_SRAMEN (0x1)
429+
430+
#define CPCHDBCR0_SPEC_DIS (0x80000000 >> 4)
431+
432+
/* T2080RM: 8.4.2.2 Enabling the CPC after Power-On Reset */
433+
/* R1 = CPC base */
434+
lis r1, CPC_BASE@h
435+
ori r1, r1, CPC_BASE@l
436+
437+
/* Set CPC SRAM control register */
438+
/* SRAM high addrress 0x0 */
439+
li r0, 0
440+
stw r0, CPCSRCR1(r1)
441+
/* SRAM low address */
442+
lis r0, L2SRAM_ADDR@h
443+
ori r0, r0, L2SRAM_ADDR@l
444+
/* Enable SRAM and set size (must match L2SRAM_SIZE) */
445+
ori r0, r0, (CPCSRCR0_SRAMSZ_256 | CPCSRCR0_SRAMEN)
446+
stw r0, CPCSRCR0(r1)
447+
448+
/* Enable memory mapped SRAM */
449+
lis r0, CPCCSR0_SRAM_ENABLE@h
450+
mbar
451+
isync
452+
stw r0, CPCCSR0(r1)
453+
mbar
454+
455+
/* Disable speculation */
456+
lwz r0, CPCHDBCR0(r1)
457+
oris r0, r0, CPCHDBCR0_SPEC_DIS@h
458+
stw r0, CPCHDBCR0(r1)
459+
460+
setup_l2_cache:
461+
/* L2 Cache Control - E6500CORERM 2.2.3 Memory-mapped registers (MMRs) */
462+
#define L2_CLUSTER_BASE(n) (CCSRBAR + 0xC20000 + (n * 0x40000))
463+
#define L2CSR0 (0x000) /* L2 Cache Control and Status 0 */
464+
#define L2CSR1 (0x004) /* L2 Cache Control and Status 1 */
465+
#define L2CFG0 (0x008) /* L2 Cache Configuration */
466+
#define L2PID(n) (0x200 + (n * 0x10)) /* L2 Cache Partitioning ID */
467+
#define L2PIR(n) (0x208 + (n * 0x10)) /* L2 Cache Partitioning Allocation */
468+
#define L2PWR(n) (0x20C + (n * 0x10)) /* L2 Cache Partitioning Way */
469+
470+
#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
471+
#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
472+
#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
473+
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
474+
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
475+
476+
/* E6500CORERM: 11.7 L2 cache state */
477+
/* R5 = L2 cluster 1 base */
478+
lis r5, L2_CLUSTER_BASE(0)@h
479+
ori r5, r5, L2_CLUSTER_BASE(0)@l
480+
/* Invalidate and clear locks */
481+
lis r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@h
482+
ori r1, r1, (L2CSR0_L2FI | L2CSR0_L2LFC)@l
434483
sync
484+
stw r1, L2CSR0(r5)
435485

436-
// TODO is this required?
437-
li r5, 33
438-
stw r5, 4(r6)
439-
440-
sync
441-
stw r4, 0(r6) /* write L2SC0 MMR to flash invalidate L2 cache and locks */
442-
l2loop:
443-
sync
444-
lwz r5, 0(r6) /* get current L2SC0 MMR value */
445-
and. r5, r5, r4 /* compare to mask to see if complete */
446-
bne l2loop
486+
/* poll till invalidate and lock bits are cleared */
487+
poll_l2_invclear:
488+
lwz r4, L2CSR0(r5)
489+
and. r4, r1, r4
490+
bne poll_l2_invclear
447491
isync
448492

449-
enable_l2_pe:
450-
lis r5, 0x4000
451-
sync
452-
stw r5, 0(r6)
453-
l2_pe_loop:
493+
/* enable L2 with parity */
454494
sync
455-
lwz r4, 0(r6)
456-
cmplw r4, r5
457-
bne l2_pe_loop
458495
isync
459-
460-
enable_l2e:
461-
lis r5, 0xC000
462-
sync
463-
stw r5, 0(r6)
464-
l2e_loop:
465-
sync
466-
lwz r4, 0(r6)
467-
cmplw r4, r5
468-
bne l2e_loop
496+
lis r4, (L2CSR0_L2E | L2CSR0_L2PE)@h
497+
stw r4, L2CSR0(r5)
469498
isync
470-
#endif /* MMU_V2 */
471-
#endif /* ENABLE_L2_CACHE */
499+
500+
/* set stash id = 32 */
501+
li r4, 32
502+
stw r4, L2CSR1(r5)
503+
504+
l2_sram_init:
505+
/* clear 8 bytes at a time */
506+
lis r2, (L2SRAM_ADDR - 8)@h
507+
ori r2, r2, (L2SRAM_ADDR - 8)@l
508+
lis r3, (L2SRAM_SIZE / 8)@h
509+
mtctr r3
510+
li r3, 0
511+
l2_sram_init_loop:
512+
stdu r3, 8(r2)
513+
bdnz l2_sram_init_loop
514+
#endif /* ENABLE_L2_CACHE && MMU_V2 */
472515

473516
#ifdef MMU_V2
474517
set_stack_as:

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