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| 1 | +/* lpc.c |
| 2 | + * |
| 3 | + * Copyright (C) 2020 wolfSSL Inc. |
| 4 | + * |
| 5 | + * This file is part of wolfBoot. |
| 6 | + * |
| 7 | + * wolfBoot is free software; you can redistribute it and/or modify |
| 8 | + * it under the terms of the GNU General Public License as published by |
| 9 | + * the Free Software Foundation; either version 2 of the License, or |
| 10 | + * (at your option) any later version. |
| 11 | + * |
| 12 | + * wolfBoot is distributed in the hope that it will be useful, |
| 13 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | + * GNU General Public License for more details. |
| 16 | + * |
| 17 | + * You should have received a copy of the GNU General Public License |
| 18 | + * along with this program; if not, write to the Free Software |
| 19 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA |
| 20 | + */ |
| 21 | + |
| 22 | +#include <stdint.h> |
| 23 | +#include <target.h> |
| 24 | +#include "image.h" |
| 25 | +#include "fsl_common.h" |
| 26 | +#include "fsl_flashiap.h" |
| 27 | +#include "fsl_power.h" |
| 28 | + |
| 29 | +static int flash_init = 0; |
| 30 | +uint32_t SystemCoreClock; |
| 31 | + |
| 32 | +#ifdef NVM_FLASH_WRITEONCE |
| 33 | +# error "wolfBoot LPC HAL: WRITEONCE support detected. Please do not define NVM_FLASH_WRITEONCE on this platform." |
| 34 | +#endif |
| 35 | + |
| 36 | +#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U |
| 37 | +#ifdef __WOLFBOOT |
| 38 | + |
| 39 | +/******************************************************************************* |
| 40 | + * Code for BOARD_BootClockPLL180M configuration (automatically generated by SDK) |
| 41 | + ******************************************************************************/ |
| 42 | +void BOARD_BootClockPLL180M(void) |
| 43 | +{ |
| 44 | + /*!< Set up the clock sources */ |
| 45 | + /*!< Set up FRO */ |
| 46 | + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ |
| 47 | + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without |
| 48 | + accidentally being below the voltage for current speed */ |
| 49 | + POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */ |
| 50 | + SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) | |
| 51 | + SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */ |
| 52 | + POWER_SetVoltageForFreq( |
| 53 | + 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ |
| 54 | + CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */ |
| 55 | + |
| 56 | + /*!< Set up SYS PLL */ |
| 57 | + const pll_setup_t pllSetup = { |
| 58 | + .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U), |
| 59 | + .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), |
| 60 | + .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), |
| 61 | + .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), |
| 62 | + .pllRate = 180000000U, |
| 63 | + .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP}; |
| 64 | + CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/ |
| 65 | + CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ |
| 66 | + /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) |
| 67 | + before calling this API since this API is implemented in ROM code */ |
| 68 | + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ |
| 69 | + |
| 70 | + /*!< Set up dividers */ |
| 71 | + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ |
| 72 | + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ |
| 73 | + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Set USB0CLKDIV divider to value 1 */ |
| 74 | + |
| 75 | + /*!< Set up clock selectors - Attach clocks to the peripheries */ |
| 76 | + CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */ |
| 77 | + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /*!< Switch USB0_CLK to FRO_HF */ |
| 78 | + SYSCON->MAINCLKSELA = |
| 79 | + ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | |
| 80 | + SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */ |
| 81 | + /* Set SystemCoreClock variable. */ |
| 82 | + SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK; |
| 83 | +} |
| 84 | + |
| 85 | +/* Assert hook needed by SDK */ |
| 86 | +void __assert_func(const char *a, int b, const char *c, const char *d) |
| 87 | +{ |
| 88 | + while(1) |
| 89 | + ; |
| 90 | +} |
| 91 | + |
| 92 | +void hal_init(void) |
| 93 | +{ |
| 94 | + BOARD_BootClockPLL180M(); |
| 95 | +} |
| 96 | + |
| 97 | +void hal_prepare_boot(void) |
| 98 | +{ |
| 99 | +} |
| 100 | + |
| 101 | +#endif |
| 102 | + |
| 103 | +#define FLASH_PAGE_SIZE 0x100 /* 256 bytes */ |
| 104 | + |
| 105 | +static uint8_t flash_page_cache[FLASH_PAGE_SIZE]; |
| 106 | + |
| 107 | +int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len) |
| 108 | +{ |
| 109 | + int w = 0; |
| 110 | + int ret; |
| 111 | + int idx = 0; |
| 112 | + uint32_t page_address; |
| 113 | + uint32_t offset; |
| 114 | + int size; |
| 115 | + while (idx < len) { |
| 116 | + page_address = ((address + idx) / FLASH_PAGE_SIZE) * FLASH_PAGE_SIZE; |
| 117 | + offset = address - page_address; |
| 118 | + size = FLASH_PAGE_SIZE - offset; |
| 119 | + if (size > (len - idx)) |
| 120 | + size = len - idx; |
| 121 | + |
| 122 | + if (size > 0) { |
| 123 | + memcpy(flash_page_cache, (void *)page_address, FLASH_PAGE_SIZE); |
| 124 | + memcpy(flash_page_cache + offset, data + idx, size); |
| 125 | + FLASHIAP_PrepareSectorForWrite(page_address / WOLFBOOT_SECTOR_SIZE, page_address / WOLFBOOT_SECTOR_SIZE); |
| 126 | + FLASHIAP_CopyRamToFlash(page_address, (uint32_t *)flash_page_cache, FLASH_PAGE_SIZE, SystemCoreClock); |
| 127 | + } |
| 128 | + idx += size; |
| 129 | + } |
| 130 | + memset(flash_page_cache, 0xFF, FLASH_PAGE_SIZE); |
| 131 | + return 0; |
| 132 | +} |
| 133 | + |
| 134 | +void RAMFUNCTION hal_flash_unlock(void) |
| 135 | +{ |
| 136 | +} |
| 137 | + |
| 138 | +void RAMFUNCTION hal_flash_lock(void) |
| 139 | +{ |
| 140 | +} |
| 141 | + |
| 142 | + |
| 143 | +int RAMFUNCTION hal_flash_erase(uint32_t address, int len) |
| 144 | +{ |
| 145 | + uint32_t start, end; |
| 146 | + start = address / WOLFBOOT_SECTOR_SIZE; |
| 147 | + end = (address + (len - 1)) / WOLFBOOT_SECTOR_SIZE; |
| 148 | + FLASHIAP_PrepareSectorForWrite(start, end); |
| 149 | + FLASHIAP_EraseSector(start, end, SystemCoreClock); |
| 150 | + return 0; |
| 151 | +} |
| 152 | + |
| 153 | + |
| 154 | + |
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