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danielinuxdgarske
danielinux
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dgarske
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Added support for STM32G0 (tested on STM32G070-Nucleo)
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‎arch.mk‎

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@@ -25,6 +25,10 @@ ifeq ($(ARCH),ARM)
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ifeq ($(TARGET),stm32l0)
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CORTEX_M0=1
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endif
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ifeq ($(TARGET),stm32g0)
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CORTEX_M0=1
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endif
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## Cortex-M CPU
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ifeq ($(CORTEX_M0),1)

‎docs/Targets.md‎

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@@ -69,6 +69,41 @@ Possible workarounds:
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- Compile ed25519 with debug (optimizations are disabled) : `make TARGET=stm32l0 DEBUG=1`
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- Use ECDSA instead (which is much faster) : `make TARGET=stm32l0 SIGN=ECC256`
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## STM32G0x0/STM32G0x1
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Example 128KB partitioning on STM32-G070:
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- Sector size: 2KB
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- Wolfboot partition size: 32KB
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- Application partition size: 45 KB
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```C
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#define WOLFBOOT_SECTOR_SIZE 0x800 /* 2 KB */
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#define WOLFBOOT_PARTITION_BOOT_ADDRESS 0x8000
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#define WOLFBOOT_PARTITION_SIZE 0xB000 /* 45 KB */
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#define WOLFBOOT_PARTITION_UPDATE_ADDRESS 0x13000
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#define WOLFBOOT_PARTITION_SWAP_ADDRESS 0x1E000
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```
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### Building
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Use `make TARGET=stm32l0`. The option `CORTEX_M0` is automatically selected for this target.
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The option `NVM_FLASH_WRITEONCE=1` is mandatory on this target, since the IAP driver does not support
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multiple writes after each erase operation.
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Compile with:
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`make TARGET=stm32g0 NVM_FLASH_WRITEONCE=1`
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#### Known issues
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With Ed25519 (default SIGN algorithm) it's not possible at the moment to compile wolfboot
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with optimizations, due to a GCC linker error complaining about a missing symbol `__gnu_thumb1_case_uqi`.
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Possible workarounds:
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- Compile ed25519 with debug (optimizations are disabled) : `make TARGET=stm32l0 DEBUG=1`
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- Use ECDSA instead (which is much faster) : `make TARGET=stm32l0 SIGN=ECC256`
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## SiFive HiFive1 RISC-V
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### Features
@@ -156,3 +191,6 @@ add-symbol-file test-app/image.elf 0x20020100
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```
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riscv64-unknown-elf-objdump -D test-app/image.elf
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```
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‎hal/stm32g0.c‎

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/* stm32g0.c
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*
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* Copyright (C) 2019 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <image.h>
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#ifndef NVM_FLASH_WRITEONCE
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# error "wolfBoot STM32G0 HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
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#endif
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/* STM32 G0 register configuration */
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/* Assembly helpers */
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#define DMB() __asm__ volatile ("dmb")
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/*** RCC ***/
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#define RCC_BASE (0x40021000)
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#define RCC_CR (*(volatile uint32_t *)(RCC_BASE + 0x00)) //RM0444 - 5.4.1
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#define RCC_PLLCFGR (*(volatile uint32_t *)(RCC_BASE + 0x0C)) //RM0444 - 5.4.4
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#define RCC_CFGR (*(volatile uint32_t *)(RCC_BASE + 0x08)) //RM0444 - 5.4.3
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#define APB1_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x3C))
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#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x40))
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_HSIRDY (1 << 10)
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#define RCC_CR_HSION (1 << 8)
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#define RCC_CFGR_SW_HSISYS 0x0
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#define RCC_CFGR_SW_PLL 0x2
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#define RCC_PLLCFGR_PLLR_EN (1 << 28) //RM0444 - 5.4.3
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#define RCC_PLLCFGR_PLLSRC_HSI16 2
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/*** APB PRESCALER ***/
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#define RCC_PRESCALER_DIV_NONE 0
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/*** FLASH ***/
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#define PWR_APB1_CLOCK_ER_VAL (1 << 28)
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#define SYSCFG_APB2_CLOCK_ER_VAL (1 << 0) //RM0444 - 5.4.15 - RCC_APBENR2 - SYSCFGEN
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#define FLASH_BASE (0x40022000) /*FLASH_R_BASE = 0x40000000UL + 0x00020000UL + 0x00002000UL */
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#define FLASH_ACR (*(volatile uint32_t *)(FLASH_BASE + 0x00)) //RM0444 - 3.7.1 - FLASH_ACR
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#define FLASH_KEY (*(volatile uint32_t *)(FLASH_BASE + 0x08)) //RM0444 - 3.7.2 - FLASH_KEYR
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#define FLASH_SR (*(volatile uint32_t *)(FLASH_BASE + 0x10)) //RM0444 - 3.7.4 - FLASH_SR
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#define FLASH_CR (*(volatile uint32_t *)(FLASH_BASE + 0x14)) //RM0444 - 3.7.5 - FLASH_CR
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#define FLASHMEM_ADDRESS_SPACE (0x08000000)
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#define FLASH_PAGE_SIZE (0x800) /* 2KB */
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/* Register values */
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#define FLASH_SR_BSY1 (1 << 16) //RM0444 - 3.7.4 - FLASH_SR
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#define FLASH_SR_SIZERR (1 << 6) //RM0444 - 3.7.4 - FLASH_SR
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#define FLASH_SR_PGAERR (1 << 5) //RM0444 - 3.7.4 - FLASH_SR
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#define FLASH_SR_WRPERR (1 << 4) //RM0444 - 3.7.4 - FLASH_SR
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#define FLASH_SR_PROGERR (1 << 3)
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#define FLASH_SR_EOP (1 << 0) //RM0444 - 3.7.4 - FLASH_SR
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#define FLASH_CR_LOCK (1 << 31) //RM0444 - 3.7.5 - FLASH_CR
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#define FLASH_CR_STRT (1 << 16) //RM0444 - 3.7.5 - FLASH_CR
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#define FLASH_CR_PER (1 << 1) //RM0444 - 3.7.5 - FLASH_CR
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#define FLASH_CR_PG (1 << 0) //RM0444 - 3.7.5 - FLASH_CR
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#define FLASH_CR_PNB_SHIFT 3 //RM0444 - 3.7.5 - FLASH_CR - PNB bits 8:3
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#define FLASH_CR_PNB_MASK 0x3f //RM0444 - 3.7.5 - FLASH_CR - PNB bits 8:3 - 6 bits
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#define FLASH_KEY1 (0x45670123)
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#define FLASH_KEY2 (0xCDEF89AB)
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static void RAMFUNCTION flash_set_waitstates(unsigned int waitstates)
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{
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uint32_t reg = FLASH_ACR;
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if ((reg & 0x03) != waitstates)
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FLASH_ACR = (reg & ~0x03) | waitstates ;
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}
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static RAMFUNCTION void flash_wait_complete(void)
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{
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while ((FLASH_SR & FLASH_SR_BSY1) == FLASH_SR_BSY1)
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;
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}
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static void RAMFUNCTION flash_clear_errors(void)
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{
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FLASH_SR |= ( FLASH_SR_SIZERR | FLASH_SR_PGAERR | FLASH_SR_WRPERR | FLASH_SR_PROGERR);
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}
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int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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int i = 0;
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uint32_t *src, *dst;
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flash_clear_errors();
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FLASH_CR |= FLASH_CR_PG;
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while (i < len) {
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flash_clear_errors();
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if ((len - i > 3) && ((((address + i) & 0x07) == 0) && ((((uint32_t)data) + i) & 0x07) == 0)) {
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src = (uint32_t *)data;
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dst = (uint32_t *)(address + FLASHMEM_ADDRESS_SPACE);
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flash_wait_complete();
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dst[i >> 2] = src[i >> 2];
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dst[(i >> 2) + 1] = src[(i >> 2) + 1];
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flash_wait_complete();
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i+=8;
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} else {
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uint32_t val[2];
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uint8_t *vbytes = (uint8_t *)(val);
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int off = (address + i) - (((address + i) >> 3) << 3);
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uint32_t base_addr = address & (~0x07); /* aligned to 64 bit */
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int u32_idx = (i >> 2);
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dst = (uint32_t *)(base_addr);
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val[0] = dst[u32_idx];
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val[1] = dst[u32_idx + 1];
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while ((off < 8) && (i < len))
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vbytes[off++] = data[i++];
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dst[u32_idx] = val[0];
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dst[u32_idx + 1] = val[1];
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flash_wait_complete();
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}
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}
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if ((FLASH_SR & FLASH_SR_EOP) == FLASH_SR_EOP);
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FLASH_SR |= FLASH_SR_EOP;
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FLASH_CR &= ~FLASH_CR_PG;
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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flash_wait_complete();
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if ((FLASH_CR & FLASH_CR_LOCK) != 0) {
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FLASH_KEY = FLASH_KEY1;
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DMB();
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FLASH_KEY = FLASH_KEY2;
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DMB();
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while ((FLASH_CR & FLASH_CR_LOCK) != 0)
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;
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}
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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flash_wait_complete();
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if ((FLASH_CR & FLASH_CR_LOCK) == 0)
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FLASH_CR |= FLASH_CR_LOCK;
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}
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int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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{
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int start = -1, end = -1;
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uint32_t end_address;
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uint32_t p;
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if (len == 0)
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return -1;
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end_address = address + len - 1;
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for (p = address; p < end_address; p += FLASH_PAGE_SIZE) {
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uint32_t reg = FLASH_CR & (~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT));
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FLASH_CR = reg | ((p >> 11) << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER;
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DMB();
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FLASH_CR |= FLASH_CR_STRT;
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flash_wait_complete();
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FLASH_CR &= ~FLASH_CR_PER;
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}
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return 0;
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}
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static void clock_pll_off(void)
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{
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uint32_t reg32;
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/* Select HSISYS as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS);
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DMB();
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/* Turn off PLL */
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RCC_CR &= ~RCC_CR_PLLON;
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DMB();
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}
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/*This implementation will setup HSI RC 16 MHz as PLL Source Mux, PLLCLK as System Clock Source*/
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static void clock_pll_on(int powersave)
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{
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uint32_t reg32;
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uint32_t cpu_freq, plln, pllm, pllq, pllp, pllr, hpre, ppre, flash_waitstates;
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/* Enable Power controller */
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APB1_CLOCK_ER |= PWR_APB1_CLOCK_ER_VAL;
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/* Select clock parameters (CPU Speed = 64MHz) */
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cpu_freq = 64000000;
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pllm = 4;
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plln = 80;
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pllp = 10;
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pllq = 5;
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pllr = 5;
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hpre = RCC_PRESCALER_DIV_NONE;
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ppre = RCC_PRESCALER_DIV_NONE;
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flash_waitstates = 2;
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flash_set_waitstates(flash_waitstates);
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/* Enable internal high-speed oscillator. */
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RCC_CR |= RCC_CR_HSION;
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DMB();
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while ((RCC_CR & RCC_CR_HSIRDY) == 0) {};
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/* Select HSISYS as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_HSISYS);
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DMB();
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/* Disable PLL */
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RCC_CR &= ~RCC_CR_PLLON;
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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*/
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reg32 = RCC_CFGR;
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reg32 &= ~(0xF0); //don't change bits [0-3] that were previously set
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RCC_CFGR = (reg32 | (hpre << 8)); //RM0444 - 5.4.3 - RCC_CFGR
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DMB();
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reg32 = RCC_CFGR;
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reg32 &= ~(0x1C00); //don't change bits [0-14]
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RCC_CFGR = (reg32 | (ppre << 12)); //RM0444 - 5.4.3 - RCC_CFGR
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DMB();
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/* Set PLL config */
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reg32 = RCC_PLLCFGR;
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reg32 |= RCC_PLLCFGR_PLLSRC_HSI16;
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reg32 |= ((pllm - 1) << 4);
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reg32 |= plln << 8;
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reg32 |= ((pllp - 1) << 17);
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// reg32 |= ((pllq - 1) << 25); /* ? - Not in in RM0464 for STM32G0x0 */
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reg32 |= ((pllr - 1) << 29);
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RCC_PLLCFGR = reg32;
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DMB();
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/* Enable PLL oscillator and wait for it to stabilize. */
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RCC_PLLCFGR |= RCC_PLLCFGR_PLLR_EN;
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RCC_CR |= RCC_CR_PLLON;
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DMB();
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while ((RCC_CR & RCC_CR_PLLRDY) == 0) {};
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/* Select PLL as SYSCLK source. */
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | RCC_CFGR_SW_PLL);
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DMB();
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/* Wait for PLL clock to be selected. */
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SW_PLL) {};
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/* SYSCFG, COMP and VREFBUF clock enable */
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APB2_CLOCK_ER |= SYSCFG_APB2_CLOCK_ER_VAL;
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}
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void hal_init(void)
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{
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clock_pll_on(0);
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}
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void hal_prepare_boot(void)
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{
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#ifdef SPI_FLASH
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spi_release();
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#endif
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clock_pll_off();
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}
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