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Added support for LPC (tested on LPC54606)
1 parent c32c5da commit 10186ca

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Lines changed: 243 additions & 1 deletion

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hal/lpc.c

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/* lpc.c
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*
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* Copyright (C) 2020 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdint.h>
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#include <target.h>
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#include "image.h"
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#include "fsl_common.h"
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#include "fsl_flashiap.h"
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#include "fsl_power.h"
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static int flash_init = 0;
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uint32_t SystemCoreClock;
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#ifndef NVM_FLASH_WRITEONCE
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# error "wolfBoot LPC HAL: no WRITEONCE support detected. Please define NVM_FLASH_WRITEONCE"
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#endif
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#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U
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#ifdef __WOLFBOOT
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/*******************************************************************************
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* Code for BOARD_BootClockPLL180M configuration (automatically generated by SDK)
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******************************************************************************/
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void BOARD_BootClockPLL180M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
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accidentally being below the voltage for current speed */
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POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
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SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
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SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */
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POWER_SetVoltageForFreq(
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180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */
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/*!< Set up SYS PLL */
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const pll_setup_t pllSetup = {
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.pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
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.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
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.pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
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.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
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.pllRate = 180000000U,
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.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
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CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
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CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
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/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
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before calling this API since this API is implemented in ROM code */
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CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
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CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */
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CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Set USB0CLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
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CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); /*!< Switch USB0_CLK to FRO_HF */
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SYSCON->MAINCLKSELA =
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((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
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SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
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}
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/* Assert hook needed by SDK */
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void __assert_func(const char *a, int b, const char *c, const char *d)
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{
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while(1)
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;
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}
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void hal_init(void)
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{
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BOARD_BootClockPLL180M();
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}
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void hal_prepare_boot(void)
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{
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}
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#endif
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#define FLASH_PAGE_SIZE 0x100 /* 256 bytes */
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static uint8_t flash_page_cache[FLASH_PAGE_SIZE];
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int RAMFUNCTION hal_flash_write(uint32_t address, const uint8_t *data, int len)
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{
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int w = 0;
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int ret;
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int idx = 0;
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uint32_t page_address;
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uint32_t offset;
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int size;
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while (idx < len) {
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page_address = (address + idx) / FLASH_PAGE_SIZE;
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offset = address - page_address;
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size = FLASH_PAGE_SIZE - offset;
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if (size > (len - idx))
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size = len - idx;
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if (size > 0) {
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memcpy(flash_page_cache, (void *)page_address, FLASH_PAGE_SIZE);
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memcpy(flash_page_cache + offset, data + idx, size);
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FLASHIAP_PrepareSectorForWrite(page_address / WOLFBOOT_SECTOR_SIZE, page_address / WOLFBOOT_SECTOR_SIZE);
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FLASHIAP_CopyRamToFlash(page_address, (uint32_t *)flash_page_cache, FLASH_PAGE_SIZE, SystemCoreClock);
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}
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idx += size;
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}
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memset(flash_page_cache, 0xFF, FLASH_PAGE_SIZE);
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return 0;
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}
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void RAMFUNCTION hal_flash_unlock(void)
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{
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}
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void RAMFUNCTION hal_flash_lock(void)
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{
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}
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int RAMFUNCTION hal_flash_erase(uint32_t address, int len)
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{
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uint32_t start, end;
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start = address / WOLFBOOT_SECTOR_SIZE;
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end = (address + (len - 1)) / WOLFBOOT_SECTOR_SIZE;
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FLASHIAP_PrepareSectorForWrite(start, end);
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FLASHIAP_EraseSector(start, end, SystemCoreClock);
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return 0;
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}
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hal/lpc.ld

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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = ##WOLFBOOT_PARTITION_BOOT_ADDRESS##
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
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}
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SECTIONS
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{
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.text :
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{
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_start_text = .;
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KEEP(*(.isr_vector))
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. = ALIGN(0x400);
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*(.text*)
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*(.rodata*)
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*(.init*)
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*(.fini*)
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. = ALIGN(4);
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_end_text = .;
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} > FLASH
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.edidx :
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{
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. = ALIGN(4);
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*(.ARM.exidx*)
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} > FLASH
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_stored_data = .;
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.data : AT (_stored_data)
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{
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_start_data = .;
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KEEP(*(.data*))
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. = ALIGN(4);
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_end_data = .;
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} > RAM
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.bss (NOLOAD) :
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{
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_start_bss = .;
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_end_bss = .;
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__bss_end__ = .;
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_end = .;
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} > RAM
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. = ALIGN(4);
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}
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END_STACK = ORIGIN(RAM) + LENGTH(RAM);

src/boot_arm.c

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void isr_reset(void) {
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register unsigned int *src, *dst;
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#if defined(PLATFORM_kinetis) || defined(PLATFORM_lpc)
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#if defined(PLATFORM_kinetis)
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/* Immediately disable Watchdog after boot */
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/* Write Keys to unlock register */
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*((volatile unsigned short *)0x4005200E) = 0xC520;

test-app/app_lpc.c

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/* main.c
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*
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* Test bare-metal boot-led-on application
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*
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* Copyright (C) 2020 wolfSSL Inc.
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*
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* This file is part of wolfBoot.
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*
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* wolfBoot is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfBoot is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include "wolfboot/wolfboot.h"
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void main(void) {
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/* Wait for reboot */
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while(1)
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;
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}
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