wolfBoot/config/openocd/openocd_stm32n6.cfg at 6585a0b2c8ba43f6e9116a56116bc3db77624d52 · wolfSSL/wolfBoot · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
# OpenOCD config for NUCLEO-N657X0-Q with MX25UM51245G NOR on XSPI2

source [find interface/stlink.cfg]
transport select swd

set CHIPNAME stm32n6x
set WORKAREASIZE 0x10000

source [find target/stm32n6x.cfg]

# Work-area above wolfBoot SRAM region
$_TARGETNAME configure -work-area-phys 0x34020000 -work-area-size $WORKAREASIZE -work-area-backup 0

# XSPI2 NOR flash bank (memory-mapped at 0x70000000, regs at 0x5802A000)
set XSPI2_BANK_ID [llength [flash list]]
flash bank $CHIPNAME.xspi2 stmqspi 0x70000000 0 0 0 $CHIPNAME.cpu 0x5802A000

# Mark VDDIO supplies valid (required for XSPI2 GPIO)
proc pwr_enable_io_supply {} {
    mmw 0x5602825C 0x00040000 0   ;# RCC_AHB4ENR: PWR clock
    mmw 0x56024834 0x00000100 0   ;# SVMCR1: VDDIO4SV
    mmw 0x56024838 0x00000100 0   ;# SVMCR2: VDDIO5SV
    mmw 0x5602483C 0x00000300 0   ;# SVMCR3: VDDIO2SV + VDDIO3SV
}

# Port N GPIO for XSPI2 (PN0-PN11, AF9, very high speed)
proc xspi2_gpio_init {} {
    mmw 0x5602825C 0x00002000 0          ;# RCC_AHB4ENR: GPION clock
    sleep 1
    mmw 0x56023400 0x00AAAAAA 0x00555555 ;# MODER: AF mode
    mmw 0x56023408 0x00FFFFFF 0          ;# OSPEEDR: very high
    mmw 0x5602340C 0 0x00FFFFFF          ;# PUPDR: no pull
    mww 0x56023420 0x99999999            ;# AFRL: AF9
    mww 0x56023424 0x00009999            ;# AFRH: AF9
}

# XSPI2 init: single-SPI, /16 prescaler, NOR reset, enter mmap mode
proc xspi2_init {} {
    mmw 0x56028260 0x00003000 0 ;# RCC_AHB5ENR: XSPI2 + XSPIM clocks
    mmw 0x56028248 0x00000008 0 ;# RCC_MISCENR: XSPI PHY comp clock
    sleep 1

    mww 0x5802A000 0x00000000   ;# CR: disable
    sleep 1
    mww 0x5802A008 0x001A0308   ;# DCR1: DLYBYP, DEVSIZE=26, CSHT=3
    mww 0x5802A00C 0x0000000F   ;# DCR2: prescaler /16
    sleep 1
    mww 0x5802A000 0x00000001   ;# CR: enable

    # NOR flash software reset (0x66 + 0x99)
    mmw 0x5802A000 0x00000002 0 ;# abort
    sleep 1
    mww 0x5802A024 0x0000000B   ;# FCR: clear flags
    mww 0x5802A100 0x00000001   ;# CCR: IMODE=single
    mww 0x5802A108 0x00000000   ;# TCR: no dummy
    mww 0x5802A110 0x00000066   ;# IR: Reset Enable
    sleep 1

    mmw 0x5802A000 0x00000002 0 ;# abort
    sleep 1
    mww 0x5802A024 0x0000000B
    mww 0x5802A100 0x00000001
    mww 0x5802A108 0x00000000
    mww 0x5802A110 0x00000099   ;# IR: Reset Memory
    sleep 10

    xspi2_mem_mapped
}

# Memory-mapped fast-read mode (single-SPI, 4-byte addr, 8 dummy cycles)
proc xspi2_mem_mapped {} {
    mmw 0x5802A000 0x00000002 0 ;# abort
    sleep 1
    mww 0x5802A000 0x30000001   ;# CR: mmap + enable
    mww 0x5802A100 0x01003101   ;# CCR: IMODE=1, ADMODE=1, ADSIZE=3, DMODE=1
    mww 0x5802A108 0x40000008   ;# TCR: DCYC=8, SSHIFT
    mww 0x5802A110 0x0000000C   ;# IR: Fast Read 4B
}

# Set NOR flash params manually (SFDP not readable in single-SPI mode)
proc xspi2_flash_set {} {
    global XSPI2_BANK_ID
    stmqspi set $XSPI2_BANK_ID MX25UM51245G 0x4000000 0x100 0x13 0 0x12 0x60 0x1000 0x21
}

# Full reinit for use when XSPI2 may already be configured
proc xspi2_reinit {} {
    global XSPI2_BANK_ID
    pwr_enable_io_supply
    xspi2_gpio_init
    xspi2_init
    xspi2_flash_set
    flash probe $XSPI2_BANK_ID
    xspi2_flash_set
}

$_TARGETNAME configure -event reset-init {
    global XSPI2_BANK_ID
    pwr_enable_io_supply
    xspi2_gpio_init
    xspi2_init
    xspi2_flash_set
    flash probe $XSPI2_BANK_ID
    # Re-set after probe (stmqspi driver quirk)
    xspi2_flash_set
}

init