Purpose: Minimal block to demonstrate the specification → RTL flow in Module 1.
If you are new to reading hardware specs, use this document in order:
- Interface (Section 2) — Tells you every port: name, direction (input/output), and width. This becomes your module’s port list in RTL.
- Behavior (Section 3) — Tells you what happens on reset, when to increment, and when to hold. This becomes the logic inside an
alwaysblock (reset first, then enable, then hold). - Timing (Section 4) — Tells you that everything is synchronous to the positive edge of
clk. That tells you to usealways @(posedge clk)and no combinational logic for the counter output.
For a step-by-step guide on understanding any spec, see module1/UNDERSTANDING_THE_SPEC.md.
For translating this spec into RTL, see module1/SPEC_TO_RTL_GUIDE.md and WALKTHROUGH.md.
- Block name:
counter - Function: 8-bit up-counter with synchronous reset and enable. Counts from 0 to 255 and wraps to 0.
| Port | Direction | Width | Description |
|---|---|---|---|
clk |
input | 1 | Clock; positive edge is active. |
rst_n |
input | 1 | Active-low synchronous reset. |
enable |
input | 1 | When high, counter increments on the next clk. |
count |
output | 8 | Current count value (0–255). |
- Reset: On the rising edge of
clk, ifrst_nis low,countis set to8'h00and remains untilrst_ngoes high. - Count: On the rising edge of
clk, ifrst_nis high andenableis high,countincrements by 1. Ifcountis 255, the next increment wraps to 0. - Hold: If
enableis low (and not in reset),countdoes not change.
- All behavior is synchronous to the positive edge of
clk. - No multi-cycle or combinational paths are specified; implementation is single-cycle update.
This spec is intentionally small so that:
- Spec → RTL: You can map each requirement to RTL (reset, enable, increment, width).
- Verification: A simple testbench can drive clk/reset/enable and check that
countmatches expectations (e.g., after N enabled cycles, count = N mod 256). - Methodology: The same flow (spec → RTL → testbench) applies to UART, SPI, and I²C in later modules.