Goal: Understand the specification → RTL design flow, design methodology, and why we verify.
This module establishes the methodology you will use for the rest of the course:
- Specification → RTL: From a written spec to synthesizable RTL
- Design methodology: How to structure and document a small block
- Intro to verification: What we verify, and why (before diving into UVM in Module 2)
No protocol-specific content (UART/SPI/I²C) or UVM yet—those come in later modules.
- Full module doc: docs/MODULE1.md
- Hands-on example: EXAMPLES.md
- Example: spec → RTL: examples/spec_to_rtl/
- UNDERSTANDING_THE_SPEC.md — How to read a specification: what to look for (interface, behavior, timing, edge cases) and a simple checklist.
- SPEC_TO_RTL_GUIDE.md — How to translate a spec into RTL step by step: ports, clock/reset, reset branch, normal behavior, edge cases, and traceability.
- examples/spec_to_rtl/WALKTHROUGH.md — Concrete walkthrough: our counter spec read section-by-section and each requirement mapped to the exact RTL in
dut/counter.v.
- Environment (Verilator + Make + C++ compiler):
verilator --version
make --version- Run the spec-to-RTL example (tiny counter: spec → RTL → simulation):
cd module1/examples/spec_to_rtl
make runSee examples/spec_to_rtl/README.md for details.
After completing this module, proceed to Module 2: Design & Verification Methodology (Part 2) — basic testbench, UVM+SV, and toolchain.