Cortex-R5/GNU: Replace MOV pc for return stack prediction

jserv · jserv · commit 72e590c6cf32 · 2026-02-05T23:28:22.000+08:00
This replaces all MOV pc,lr and MOV pc,r3 return instructions with BX lr
and BX r3 across the Cortex-R5 GNU port. Remove the now-unnecessary
__THUMB_INTERWORK conditional compilation blocks.

On ARMv7-R, BX is the architecturally correct return instruction:
it handles ARM/Thumb interworking natively and feeds Cortex-R5 return
stack predictor, whereas MOV pc,lr is treated as generic data move that
bypasses branch prediction.

Validated against Cortex-R5 TRM (DDI 0460D) and ARMv7-A/R ARM
(DDI 0406C Section A2.3). Exception return via LDMIA {...,pc}^
correctly left untouched.
diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S
@@ -99,10 +99,6 @@ _tx_thread_fiq_nesting_end:
     ORR     r0, r0, #FIQ_MODE_BITS              @ Build IRQ mode CPSR
     MSR     CPSR_c, r0                          @ Reenter IRQ mode
 
-#ifdef __THUMB_INTERWORK
     BX      r3                                  @ Return to caller
-#else
-    MOV     pc, r3                              @ Return to caller
-#endif
 @}
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S
@@ -91,10 +91,6 @@ _tx_thread_fiq_nesting_start:
                                                 @   and push r1 just to keep 8-byte alignment
     BIC     r0, r0, #FIQ_DISABLE                @ Build enable FIQ CPSR
     MSR     CPSR_c, r0                          @ Enter system mode
-#ifdef __THUMB_INTERWORK
     BX      r3                                  @ Return to caller
-#else
-    MOV     pc, r3                              @ Return to caller
-#endif
 @}
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S
@@ -100,10 +100,6 @@ _tx_thread_interrupt_control:
 @
     MSR     CPSR_c, r1                  @ Setup new CPSR
     BIC     r0, r3, r2                  @ Return previous interrupt mask
-#ifdef __THUMB_INTERWORK
     BX      lr                          @ Return to caller
-#else
-    MOV     pc, lr                      @ Return to caller
-#endif
 @}
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S
@@ -98,11 +98,7 @@ _tx_thread_interrupt_disable:
     DMB                                         @ Memory barrier (acquire semantics)
     ISB                                         @ Flush pipeline
 
-#ifdef __THUMB_INTERWORK
     BX      lr                                  @ Return to caller
-#else
-    MOV     pc, lr                              @ Return to caller
-#endif
 @}
 
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S
@@ -90,10 +90,6 @@ _tx_thread_interrupt_restore:
     DMB                                         @ Memory barrier (release semantics)
     MSR     CPSR_c, r0                          @ Setup new CPSR
     ISB                                         @ Synchronize context
-#ifdef __THUMB_INTERWORK
     BX      lr                                  @ Return to caller
-#else
-    MOV     pc, lr                              @ Return to caller
-#endif
 @}
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S
@@ -98,10 +98,6 @@ _tx_thread_irq_nesting_end:
     BIC     r0, r0, #MODE_MASK                  @ Clear mode bits
     ORR     r0, r0, #IRQ_MODE_BITS              @ Build IRQ mode CPSR
     MSR     CPSR_c, r0                          @ Reenter IRQ mode
-#ifdef __THUMB_INTERWORK
     BX      r3                                  @ Return to caller
-#else
-    MOV     pc, r3                              @ Return to caller
-#endif
 @}
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S
@@ -91,10 +91,6 @@ _tx_thread_irq_nesting_start:
                                                 @   and push r1 just to keep 8-byte alignment
     BIC     r0, r0, #IRQ_DISABLE                @ Build enable IRQ CPSR
     MSR     CPSR_c, r0                          @ Enter system mode
-#ifdef __THUMB_INTERWORK
     BX      r3                                  @ Return to caller
-#else
-    MOV     pc, r3                              @ Return to caller
-#endif
 @}
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_schedule.S b/ports/cortex_r5/gnu/src/tx_thread_schedule.S
@@ -190,11 +190,7 @@ _tx_skip_solicited_vfp_restore:
     LDMIA   sp!, {r4-r11, lr}                   @ Return to thread synchronously
     MSR     CPSR_cxsf, r0                       @ Recover CPSR
 @
-#ifdef __THUMB_INTERWORK
     BX      lr                                  @ Return to caller
-#else
-    MOV     pc, lr                              @ Return to caller
-#endif
 @
 @}
 @
diff --git a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S
@@ -161,11 +161,7 @@ _tx_thread_stack_build:
 @
     STR     r2, [r0, #8]                    @ Save stack pointer in thread's
                                             @   control block
-#ifdef __THUMB_INTERWORK
     BX      lr                              @ Return to caller
-#else
-    MOV     pc, lr                          @ Return to caller
-#endif
 @}
 
 
diff --git a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S
@@ -114,7 +114,7 @@ _tx_thread_vectored_context_save:
     POP     {lr}                                @ Recover ISR lr
 #endif
 
-    MOV     pc, lr                              @ Return to caller
+    BX      lr                                  @ Return to caller
 @
 __tx_thread_not_nested_save:
 @    }
@@ -154,7 +154,7 @@ __tx_thread_not_nested_save:
     POP     {lr}                                @ Recover ISR lr
 #endif
 
-    MOV     pc, lr                              @ Return to caller
+    BX      lr                                  @ Return to caller
 @
 @    }
 @    else
@@ -179,7 +179,7 @@ __tx_thread_idle_system_save:
 #endif
 
     ADD     sp, sp, #32                         @ Recover saved registers
-    MOV     pc, lr                              @ Return to caller
+    BX      lr                                  @ Return to caller
 @
 @    }
 @}
diff --git a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S
@@ -261,11 +261,7 @@ __tx_timer_not_ts_expiration:
 @
 __tx_timer_nothing_expired:
 @
-#ifdef __THUMB_INTERWORK
     BX      lr                                  @ Return to caller
-#else
-    MOV     pc, lr                              @ Return to caller
-#endif
 @
 @}
 

Original file line number	Diff line number	Diff line change
`@@ -190,11 +190,7 @@ _tx_skip_solicited_vfp_restore:`
`190`	`190`	`LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously`
`191`	`191`	`MSR CPSR_cxsf, r0 @ Recover CPSR`
`192`	`192`	`@`
`193`		`-#ifdef __THUMB_INTERWORK`
`194`	`193`	`BX lr @ Return to caller`
`195`		`-#else`
`196`		`- MOV pc, lr @ Return to caller`
`197`		`-#endif`
`198`	`194`	`@`
`199`	`195`	`@}`
`200`	`196`	`@`