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Jer6yjserv
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Fix RV64 context_restore bug when F/D extension is enabled
Signed-off-by: Jim Huang <jserv@ccns.ncku.edu.tw>
1 parent 28e843c commit 2d4e183

2 files changed

Lines changed: 4 additions & 4 deletions

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ports/risc-v64/gnu/src/tx_thread_context_restore.S

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,7 @@ _tx_thread_context_restore:
150150
csrw mepc, t0 // Setup mepc
151151
li t0, 0x1880 // Prepare MPIP
152152
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
153-
li t1, 1<<13
153+
li t1, 1 << 13
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or t0, t1, t0
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#endif
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csrw mstatus, t0 // Enable MPIP
@@ -264,8 +264,8 @@ _tx_thread_no_preempt_restore:
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csrw mepc, t0 // Setup mepc
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li t0, 0x1880 // Prepare MPIP
266266
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
267-
li t1, 1<<13
268-
or t0, t1, t0
267+
li t1, 1 << 13
268+
or t0, t1, t0
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#endif
270270
csrw mstatus, t0 // Enable MPIP
271271

ports/risc-v64/gnu/src/tx_thread_schedule.S

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ _tx_thread_schedule_loop:
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csrw mepc, t0 // Store mepc
203203
li t0, 0x1880 // Prepare MPIP
204204
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
205-
li t1, 1<<13
205+
li t1, 1 << 13
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or t0, t1, t0
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#endif
208208
csrw mstatus, t0 // Enable MPIP

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