Fix Cortex-R5 SVC stack init for VFP alignment

Critical bugs discovered:
1. SVC stack was never initialized, causing potential alignment faults
   for VFP double-precision operations (VSTMDB/VLDMIA in SVC mode)
2. Wrong base pointer: loaded _sp (DDR) instead of _stack_top (ATCM)
   Result: Stacks placed in external memory, not TCM
3. Wrong initialization order: assembly didn't match linker layout
   Result: Stack overlap and memory corruption
4. Conditional bug: When TX_ENABLE_IRQ_NESTING disabled, code skipped
   SYS region, placing FIQ/IRQ in wrong memory regions
5. ARM compliance issues: Full CPSR writes, missing ISB barriers

Fixes applied:

Assembly (tx_initialize_low_level.S):
- Changed base from _sp to _stack_top (ATCM)
- Reordered initialization: SVC → SYS → FIQ → IRQ (matches linker)
- Added SVC_STACK_SIZE = 1024 and SVC stack initialization
- Added #else clause to always subtract SYS_STACK_SIZE (maintain layout)
- Changed MSR CPSR to MSR CPSR_c (control field only)
- Added ISB after each mode change (ARMv7-R best practice)
- Removed unnecessary SUB #1 before BIC eclipse-threadx#7

Linker (sample_threadx_tcm.ld):
- Added .stack_svc section (1KB, ALIGN(8), in ATCM)
- Added SVC_STACK_SIZE constant
- Exported _sp_svc symbol

ARM Reference: ARMv7-R Architecture Manual DDI 0406C
- Section A8.8.383: VSTM alignment requirements (8-byte for D0-D15)
- Section B1.3.3: Processor modes and banked SP registers
- Section A3.8.3: ISB instruction synchronization barrier

Author: jserv

ports/cortex_r5/gnu/example_build/sample_threadx_tcm.ld

@@ -37,12 +37,14 @@ OUTPUT_ARCH(arm)
  * Adjust these based on your application requirements:
  *   - FIQ_STACK_SIZE: Fast Interrupt stack (typically 512-1024 bytes)
  *   - IRQ_STACK_SIZE: Standard interrupt stack (typically 1024-2048 bytes)
+ *   - SVC_STACK_SIZE: Supervisor mode stack for VFP preemption (1024 bytes minimum)
  *   - SYS_STACK_SIZE: System mode stack for nested interrupts (1024-2048 bytes)
  *
- * Total ATCM requirement: ~2560 bytes for stacks + critical data
+ * Total ATCM requirement: ~3584 bytes for stacks + critical data
  */
 FIQ_STACK_SIZE = 512;
 IRQ_STACK_SIZE = 1024;
+SVC_STACK_SIZE = 1024;  /* CRITICAL: Required for VFP context save/restore alignment */
 SYS_STACK_SIZE = 1024;  /* Only used if TX_ENABLE_IRQ_NESTING is defined */
 
 /*
@@ -113,12 +115,25 @@ SECTIONS
         _stack_sys_end = .;
     } > ATCM
 
+    /* SVC Stack - Used for interrupt preemption with VFP context switching
+     * CRITICAL: Must be 8-byte aligned for VSTMDB/VLDMIA double-precision VFP operations
+     * Context save in tx_thread_context_restore.S:205 switches to SVC mode and uses this stack
+     * Size: 1KB minimum for nested preemption with full VFP context (200 bytes per frame)
+     */
+    .stack_svc (NOLOAD) : ALIGN(8)
+    {
+        _stack_svc_start = .;
+        . += SVC_STACK_SIZE;
+        _stack_svc_end = .;
+    } > ATCM
+
     /* Export stack pointers for use in tx_initialize_low_level.S */
     _sp_irq = _stack_irq_end;
     _sp_fiq = _stack_fiq_end;
+    _sp_svc = _stack_svc_end;
     _sp_sys = _stack_sys_end;
     _stack_bottom = _stack_irq_start;
-    _stack_top = _stack_sys_end;
+    _stack_top = _stack_svc_end;
 
     /*
      * Code Sections in DDR

ports/cortex_r5/gnu/example_build/tx_initialize_low_level.S

@@ -38,6 +38,7 @@ FIQ_MODE        =       0xD1                    @ Disable IRQ/FIQ FIQ mode
 SYS_MODE        =       0xDF                    @ Disable IRQ/FIQ SYS mode
 FIQ_STACK_SIZE  =       512                     @ FIQ stack size
 IRQ_STACK_SIZE  =       1024                    @ IRQ stack size
+SVC_STACK_SIZE  =       1024                    @ SVC stack size (for VFP preemption)
 SYS_STACK_SIZE  =       1024                    @ System stack size
 @
 @
@@ -122,38 +123,63 @@ _tx_initialize_low_level:
 @    /* We must be in SVC mode at this point!  */
 @
 @    /* Setup various stack pointers.  */
+@    /* CRITICAL: Initialize top-to-bottom to match linker script memory layout */
+@    /* Memory layout (ATCM): IRQ (low) → FIQ → SYS → SVC (high) */
+@    /* Initialization order: SVC (high) → SYS → FIQ → IRQ (low) */
 @
-    LDR     r1, =_sp                            @ Get pointer to stack area
+    LDR     r1, =_stack_top                     @ Start at top of ATCM (SVC end)
+@
+@    /* Setup SVC stack (highest address) - CRITICAL for VFP alignment */
+@
+    LDR     r2, =SVC_STACK_SIZE                 @ Pickup SVC stack size
+    MOV     r0, #SVC_MODE                       @ Build SVC mode CPSR
+    MSR     CPSR_c, r0                          @ Enter SVC mode (control field only)
+    ISB                                         @ Instruction barrier after mode change
+    BIC     r1, r1, #7                          @ Ensure 8-byte alignment for VFP operations
+    MOV     sp, r1                              @ Setup SVC stack pointer (CRITICAL for VFP)
+    SUB     r1, r1, r2                          @ Move down to SYS top
 
-#ifdef TX_ENABLE_IRQ_NESTING 
+#ifdef TX_ENABLE_IRQ_NESTING
 @
 @    /* Setup the system mode stack for nested interrupt support  */
 @
     LDR     r2, =SYS_STACK_SIZE                 @ Pickup stack size
     MOV     r3, #SYS_MODE                       @ Build SYS mode CPSR
-    MSR     CPSR_c, r3                          @ Enter SYS mode
-    SUB     r1, r1, #1                          @ Backup 1 byte
+    MSR     CPSR_c, r3                          @ Enter SYS mode (control field only)
+    ISB                                         @ Instruction barrier after mode change
     BIC     r1, r1, #7                          @ Ensure 8-byte alignment
     MOV     sp, r1                              @ Setup SYS stack pointer
-    SUB     r1, r1, r2                          @ Calculate start of next stack
+    SUB     r1, r1, r2                          @ Move down to FIQ top
+#else
+@
+@    /* Skip SYS stack setup but reserve space to match linker layout */
+@
+    LDR     r2, =SYS_STACK_SIZE                 @ Pickup stack size
+    SUB     r1, r1, r2                          @ Skip over SYS region (maintain layout)
 #endif
-
+@
+@    /* Setup FIQ stack */
+@
     LDR     r2, =FIQ_STACK_SIZE                 @ Pickup stack size
     MOV     r0, #FIQ_MODE                       @ Build FIQ mode CPSR
-    MSR     CPSR, r0                            @ Enter FIQ mode
-    SUB     r1, r1, #1                          @ Backup 1 byte
+    MSR     CPSR_c, r0                          @ Enter FIQ mode (control field only)
+    ISB                                         @ Instruction barrier after mode change
     BIC     r1, r1, #7                          @ Ensure 8-byte alignment
     MOV     sp, r1                              @ Setup FIQ stack pointer
-    SUB     r1, r1, r2                          @ Calculate start of next stack
+    SUB     r1, r1, r2                          @ Move down to IRQ top
+@
+@    /* Setup IRQ stack (lowest address) */
+@
     LDR     r2, =IRQ_STACK_SIZE                 @ Pickup IRQ stack size
     MOV     r0, #IRQ_MODE                       @ Build IRQ mode CPSR
-    MSR     CPSR, r0                            @ Enter IRQ mode
-    SUB     r1, r1, #1                          @ Backup 1 byte
+    MSR     CPSR_c, r0                          @ Enter IRQ mode (control field only)
+    ISB                                         @ Instruction barrier after mode change
     BIC     r1, r1, #7                          @ Ensure 8-byte alignment
     MOV     sp, r1                              @ Setup IRQ stack pointer
-    SUB     r3, r1, r2                          @ Calculate end of IRQ stack
-    MOV     r0, #SVC_MODE                       @ Build SVC mode CPSR
-    MSR     CPSR, r0                            @ Enter SVC mode
+    SUB     r3, r1, r2                          @ Calculate bottom of IRQ stack
+@
+@    /* Verify stack does not overflow into other memory.  */
+@
     LDR     r2, =_stack_bottom                  @ Pickup stack bottom
     CMP     r3, r2                              @ Compare the current stack end with the bottom
 _stack_error_loop: