fix: warm/cold boot low power behavior

Author: zfields

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.cpp

@@ -158,6 +158,14 @@ WEAK void SystemClock_Config(void)
   */
   __HAL_RCC_PWR_CLK_ENABLE();
 
+  /* DBGMCU->CR debug bits (DBG_SLEEP, DBG_STOP, DBG_STANDBY) survive NRST
+   * and are cleared only on VDD cycle. A prior SWD session can latch them,
+   * leaving the debug subsystem clocked in STOP/STANDBY on every subsequent
+   * warm reboot (hundreds of uA). Scrub them on every boot.
+   */
+  CLEAR_BIT(DBGMCU->CR,
+            DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY);
+
   /* Voltage scaling - Scale 1 required for SYSCLK = 80 MHz
    * RM0394 s.5.1.7: VOS2 supports up to 26 MHz only
    */

variants/STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY/variant_SWAN_R5.cpp

@@ -190,6 +190,14 @@ WEAK void SystemClock_Config(void)
   */
   __HAL_RCC_PWR_CLK_ENABLE();
 
+  /* DBGMCU->CR debug bits (DBG_SLEEP, DBG_STOP, DBG_STANDBY) survive NRST
+   * and are cleared only on VDD cycle. A prior SWD session can latch them,
+   * leaving the debug subsystem clocked in STOP/STANDBY on every subsequent
+   * warm reboot (hundreds of uA). Scrub them on every boot.
+   */
+  CLEAR_BIT(DBGMCU->CR,
+            DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY);
+
   /* Voltage scaling - Scale 1 Boost required for SYSCLK = 120 MHz
    * RM0432 s.5.1.8: "In Range 1 boost mode (R1MODE = 0), the maximum system
    * clock frequency is 120 MHz"

variants/STM32U5xx/U575O(G-I)YxQ_U585OIYxQ/variant_HERON.cpp

@@ -206,6 +206,19 @@ WEAK void SystemClock_Config(void)
   */
   __HAL_RCC_PWR_CLK_ENABLE();
 
+  /** Clear DBGMCU low-power-mode latch bits
+   *
+   * ST-Link and IDEs set DBG_STOP and DBG_STANDBY on debugger attach to keep
+   * the SWD link alive across low-power mode entry. These bits survive NRST,
+   * watchdog, and software reset, and only clear on a true VDD cycle. If
+   * left set in the field, the debug subsystem stays clocked in STOP2 and
+   * adds hundreds of uA.
+   *
+   * On STM32U5 only DBG_STOP and DBG_STANDBY exist in DBGMCU->CR; there is
+   * no DBG_SLEEP bit on the Cortex-M33 debug architecture.
+   */
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY);
+
   /** Select SMPS as the Vcore regulator
    *
    * The STM32U575OIY6QTR (Q-suffix) exposes the dedicated SMPS pinout, and