|
86 | 86 |
|
87 | 87 | #define DSI_VID_MODE_CFG 0x38 |
88 | 88 | #define VPG_EN BIT(16) |
| 89 | +#define LP_CMD_EN BIT(15) |
89 | 90 | #define FRAME_BTA_ACK BIT(14) |
90 | 91 | #define LP_HFP_EN BIT(13) |
91 | 92 | #define LP_HBP_EN BIT(12) |
92 | | -#define ENABLE_LOW_POWER (0xf << 8) |
93 | | -#define ENABLE_LOW_POWER_MASK (0xf << 8) |
| 93 | +#define LP_VACT_EN BIT(11) |
| 94 | +#define LP_VFP_EN BIT(10) |
| 95 | +#define LP_VBP_EN BIT(9) |
| 96 | +#define LP_VSA_EN BIT(8) |
94 | 97 | #define VID_MODE_TYPE_BURST_SYNC_PULSES 0x0 |
95 | 98 | #define VID_MODE_TYPE_BURST_SYNC_EVENTS 0x1 |
96 | 99 | #define VID_MODE_TYPE_BURST 0x2 |
@@ -515,6 +518,16 @@ static inline void mipi_dphy_rstz_deassert(struct dw_mipi_dsi *dsi) |
515 | 518 | udelay(1); |
516 | 519 | } |
517 | 520 |
|
| 521 | +static inline void dpishutdn_assert(struct dw_mipi_dsi *dsi) |
| 522 | +{ |
| 523 | + grf_field_write(dsi, DPISHUTDN, 1); |
| 524 | +} |
| 525 | + |
| 526 | +static inline void dpishutdn_deassert(struct dw_mipi_dsi *dsi) |
| 527 | +{ |
| 528 | + grf_field_write(dsi, DPISHUTDN, 0); |
| 529 | +} |
| 530 | + |
518 | 531 | static inline void testif_testclk_assert(struct dw_mipi_dsi *dsi) |
519 | 532 | { |
520 | 533 | regmap_update_bits(dsi->regmap, DSI_PHY_TST_CTRL0, |
@@ -653,6 +666,24 @@ static void mipi_dphy_power_off(struct dw_mipi_dsi *dsi) |
653 | 666 | phy_power_off(dsi->dphy.phy); |
654 | 667 | } |
655 | 668 |
|
| 669 | +static int dw_mipi_dsi_turn_on_peripheral(struct dw_mipi_dsi *dsi) |
| 670 | +{ |
| 671 | + dpishutdn_assert(dsi); |
| 672 | + udelay(20); |
| 673 | + dpishutdn_deassert(dsi); |
| 674 | + |
| 675 | + return 0; |
| 676 | +} |
| 677 | + |
| 678 | +static int dw_mipi_dsi_shutdown_peripheral(struct dw_mipi_dsi *dsi) |
| 679 | +{ |
| 680 | + dpishutdn_deassert(dsi); |
| 681 | + udelay(20); |
| 682 | + dpishutdn_assert(dsi); |
| 683 | + |
| 684 | + return 0; |
| 685 | +} |
| 686 | + |
656 | 687 | static void dw_mipi_dsi_host_power_on(struct dw_mipi_dsi *dsi) |
657 | 688 | { |
658 | 689 | regmap_write(dsi->regmap, DSI_PWR_UP, POWERUP); |
@@ -923,6 +954,28 @@ static ssize_t dw_mipi_dsi_transfer(struct dw_mipi_dsi *dsi, |
923 | 954 | int val; |
924 | 955 | int len = msg->tx_len; |
925 | 956 |
|
| 957 | + switch (msg->type) { |
| 958 | + case MIPI_DSI_SHUTDOWN_PERIPHERAL: |
| 959 | + return dw_mipi_dsi_shutdown_peripheral(dsi); |
| 960 | + case MIPI_DSI_TURN_ON_PERIPHERAL: |
| 961 | + return dw_mipi_dsi_turn_on_peripheral(dsi); |
| 962 | + case MIPI_DSI_DCS_SHORT_WRITE: |
| 963 | + case MIPI_DSI_DCS_SHORT_WRITE_PARAM: |
| 964 | + case MIPI_DSI_DCS_LONG_WRITE: |
| 965 | + case MIPI_DSI_DCS_READ: |
| 966 | + case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: |
| 967 | + case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: |
| 968 | + case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: |
| 969 | + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: |
| 970 | + case MIPI_DSI_GENERIC_LONG_WRITE: |
| 971 | + case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: |
| 972 | + case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: |
| 973 | + case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: |
| 974 | + break; |
| 975 | + default: |
| 976 | + return -EINVAL; |
| 977 | + } |
| 978 | + |
926 | 979 | /* create a packet to the DSI protocol */ |
927 | 980 | ret = mipi_dsi_create_packet(&packet, msg); |
928 | 981 | if (ret) { |
@@ -1003,7 +1056,13 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) |
1003 | 1056 | { |
1004 | 1057 | u32 val; |
1005 | 1058 |
|
1006 | | - val = LP_HFP_EN | ENABLE_LOW_POWER; |
| 1059 | + val = LP_VACT_EN | LP_VFP_EN | LP_VBP_EN | LP_VSA_EN | LP_CMD_EN; |
| 1060 | + |
| 1061 | + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) |
| 1062 | + val |= LP_HFP_EN; |
| 1063 | + |
| 1064 | + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) |
| 1065 | + val |= LP_HBP_EN; |
1007 | 1066 |
|
1008 | 1067 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) |
1009 | 1068 | val |= VID_MODE_TYPE_BURST; |
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