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Commit 34b8719

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finley1226ZhengShunQian
finley1226
authored and
ZhengShunQian
committed
clk: rockchip: rk3308: Add some new clocks
Add clock for pwm1, pwm2, can, owire. Change-Id: Id9a9330da359c3d2c53ae0f0f2e41cf4ff495cc4 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
1 parent d370f9b commit 34b8719

3 files changed

Lines changed: 39 additions & 12 deletions

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‎arch/arm64/boot/dts/rockchip/rk3308.dtsi‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -609,7 +609,7 @@
609609
#pwm-cells = <3>;
610610
pinctrl-names = "active";
611611
pinctrl-0 = <&pwm0_pin>;
612-
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
612+
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
613613
clock-names = "pwm", "pclk";
614614
status = "disabled";
615615
};
@@ -620,7 +620,7 @@
620620
#pwm-cells = <3>;
621621
pinctrl-names = "active";
622622
pinctrl-0 = <&pwm1_pin>;
623-
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
623+
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
624624
clock-names = "pwm", "pclk";
625625
status = "disabled";
626626
};
@@ -631,7 +631,7 @@
631631
#pwm-cells = <3>;
632632
pinctrl-names = "active";
633633
pinctrl-0 = <&pwm2_pin>;
634-
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
634+
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
635635
clock-names = "pwm", "pclk";
636636
status = "disabled";
637637
};
@@ -642,7 +642,7 @@
642642
#pwm-cells = <3>;
643643
pinctrl-names = "active";
644644
pinctrl-0 = <&pwm3_pin>;
645-
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
645+
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
646646
clock-names = "pwm", "pclk";
647647
status = "disabled";
648648
};

‎drivers/clk/rockchip/clk-rk3308.c‎

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -403,9 +403,15 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
403403
RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS,
404404
RK3308_CLKGATE_CON(3), 0, GFLAGS),
405405

406-
COMPOSITE(SCLK_PWM, "clk_pwm", mux_dpll_vpll0_xin24m_p, 0,
406+
COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
407407
RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
408408
RK3308_CLKGATE_CON(3), 1, GFLAGS),
409+
COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
410+
RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS,
411+
RK3308_CLKGATE_CON(15), 0, GFLAGS),
412+
COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
413+
RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
414+
RK3308_CLKGATE_CON(15), 1, GFLAGS),
409415

410416
COMPOSITE(SCLK_SPI0, "clk_isp0", mux_dpll_vpll0_xin24m_p, 0,
411417
RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
@@ -548,6 +554,10 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
548554
MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT,
549555
RK3308_CLKSEL_CON(43), 15, 1, MFLAGS),
550556

557+
COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,
558+
RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS,
559+
RK3308_CLKGATE_CON(8), 15, GFLAGS),
560+
551561
/*
552562
* Clock-Architecture Diagram 5
553563
*/
@@ -864,7 +874,7 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
864874
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS),
865875
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS),
866876
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS),
867-
GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
877+
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
868878
GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
869879
GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
870880
GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS),
@@ -888,6 +898,10 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
888898
GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS),
889899
GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS),
890900
GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS),
901+
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS),
902+
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS),
903+
GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS),
904+
GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
891905
};
892906

893907
static const char *const rk3308_critical_clocks[] __initconst = {

‎include/dt-bindings/clock/rk3308-cru.h‎

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@
3636
#define SCLK_I2C1 23
3737
#define SCLK_I2C2 24
3838
#define SCLK_I2C3 25
39-
#define SCLK_PWM 26
39+
#define SCLK_PWM0 26
4040
#define SCLK_SPI0 27
4141
#define SCLK_SPI1 28
4242
#define SCLK_SPI2 29
@@ -130,9 +130,12 @@
130130
#define SCLK_I2S3_8CH_RX_SRC 117
131131
#define SCLK_I2S0_2CH_SRC 118
132132
#define SCLK_I2S1_2CH_SRC 119
133+
#define SCLK_PWM1 120
134+
#define SCLK_PWM2 121
135+
#define SCLK_OWIRE 122
133136

134137
/* dclk */
135-
#define DCLK_VOP 120
138+
#define DCLK_VOP 125
136139

137140
/* aclk */
138141
#define ACLK_BUS_SRC 130
@@ -188,7 +191,7 @@
188191
#define PCLK_I2C1 203
189192
#define PCLK_I2C2 204
190193
#define PCLK_I2C3 205
191-
#define PCLK_PWM 206
194+
#define PCLK_PWM0 206
192195
#define PCLK_SPI0 207
193196
#define PCLK_SPI1 208
194197
#define PCLK_SPI2 209
@@ -213,8 +216,12 @@
213216
#define PCLK_CRU 228
214217
#define PCLK_OTP_PHY 229
215218
#define PCLK_CPU_BOOST 230
219+
#define PCLK_PWM1 231
220+
#define PCLK_PWM2 232
221+
#define PCLK_CAN 233
222+
#define PCLK_OWIRE 234
216223

217-
#define CLK_NR_CLKS (PCLK_CPU_BOOST + 1)
224+
#define CLK_NR_CLKS (PCLK_OWIRE + 1)
218225

219226
/* soft-reset indices */
220227

@@ -284,8 +291,8 @@
284291
#define SRST_I2C2 59
285292
#define SRST_I2C3_P 60
286293
#define SRST_I2C3 61
287-
#define SRST_PWM_P 62
288-
#define SRST_PWM 63
294+
#define SRST_PWM0_P 62
295+
#define SRST_PWM0 63
289296

290297
/* cru_softrst_con4 */
291298
#define SRST_SPI0_P 64
@@ -325,6 +332,10 @@
325332
/* cru_softrst_con6 */
326333
#define SRST_CPU_BOOST 96
327334
#define SRST_CPU_BOOST_P 97
335+
#define SRST_PWM1_P 98
336+
#define SRST_PWM1 99
337+
#define SRST_PWM2_P 100
338+
#define SRST_PWM2 101
328339
#define SRST_PERI_NIU_A 104
329340
#define SRST_PERI_NIU_H 105
330341
#define SRST_PERI_NIU_p 106
@@ -349,6 +360,8 @@
349360
#define SRST_NANDC_H 123
350361
#define SRST_NANDC_N 124
351362
#define SRST_MAC_A 125
363+
#define SRST_CAN_P 126
364+
#define SRST_OWIRE_P 127
352365

353366
/* cru_softrst_con8 */
354367
#define SRST_AUDIO_NIU_H 128

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