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x86: Handle CPU exceptions, read registers properly
1 parent 71ba4d1 commit ac72311

5 files changed

Lines changed: 364 additions & 175 deletions

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‎src/arch/i686/CMakeLists.txt‎

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@@ -6,6 +6,7 @@ set(ARCH_OBJECTS
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profile_intr.asm
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apic_asm.asm
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arch_start.asm
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exceptions.asm
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interrupts.asm
1011
)
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‎src/arch/i686/exceptions.asm‎

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; This file is a part of the IncludeOS unikernel - www.includeos.org
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;
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; Copyright 2015 Oslo and Akershus University College of Applied Sciences
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; and Alfred Bratterud
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;
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; Licensed under the Apache License, Version 2.0 (the "License");
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; you may not use this file except in compliance with the License.
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; You may obtain a copy of the License at
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;
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; http://www.apache.org/licenses/LICENSE-2.0
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;
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; Unless required by applicable law or agreed to in writing, software
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; distributed under the License is distributed on an "AS IS" BASIS,
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; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; See the License for the specific language governing permissions and
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; limitations under the License.
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[BITS 32]
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extern cpu_exception
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SECTION .bss
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i386_registers:
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resb 4*16
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%macro CPU_EXCEPT 1
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global __cpu_except_%1:function
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__cpu_except_%1:
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call save_cpu_regs
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;; new stack frame
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push ebp
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mov ebp, esp
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;; enter panic
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push 0
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push %1
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push i386_registers
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call cpu_exception
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%endmacro
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%macro CPU_EXCEPT_CODE 1
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global __cpu_except_%1:function
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__cpu_except_%1:
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call save_cpu_regs
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;; pop error code
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pop edx
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;; new stack frame
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push ebp
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mov ebp, esp
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;; enter panic
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push edx
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push %1
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push i386_registers
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call cpu_exception
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%endmacro
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SECTION .text
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%define regs(r) [i386_registers + r]
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save_cpu_regs:
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mov regs( 0), eax
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mov regs( 4), ebx
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mov regs( 8), ecx
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mov regs(12), edx
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mov regs(16), ebp
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mov eax, [esp + 16] ;; esp
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mov regs(20), eax
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mov regs(24), esi
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mov regs(28), edi
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mov eax, [esp + 4] ;; eip
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mov regs(32), eax
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pushf ;; eflags
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pop DWORD regs(36)
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ret
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CPU_EXCEPT 0
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CPU_EXCEPT 1
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CPU_EXCEPT 2
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CPU_EXCEPT 3
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CPU_EXCEPT 4
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CPU_EXCEPT 5
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CPU_EXCEPT 6
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CPU_EXCEPT 7
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CPU_EXCEPT_CODE 8
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CPU_EXCEPT 9
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CPU_EXCEPT_CODE 10
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CPU_EXCEPT_CODE 11
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CPU_EXCEPT_CODE 12
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CPU_EXCEPT_CODE 13
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CPU_EXCEPT_CODE 14
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CPU_EXCEPT 15
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CPU_EXCEPT 16
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CPU_EXCEPT_CODE 17
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CPU_EXCEPT 18
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CPU_EXCEPT 19
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CPU_EXCEPT 20
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CPU_EXCEPT_CODE 30

‎src/arch/x86_64/CMakeLists.txt‎

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apic_asm.asm
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apic_longmode.asm
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arch_start.asm
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exceptions.asm
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interrupts.asm
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fiber_asm.asm
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ist.cpp

‎src/arch/x86_64/exceptions.asm‎

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; This file is a part of the IncludeOS unikernel - www.includeos.org
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;
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; Copyright 2015 Oslo and Akershus University College of Applied Sciences
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; and Alfred Bratterud
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;
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; Licensed under the Apache License, Version 2.0 (the "License");
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; you may not use this file except in compliance with the License.
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; You may obtain a copy of the License at
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;
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; http://www.apache.org/licenses/LICENSE-2.0
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;
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; Unless required by applicable law or agreed to in writing, software
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; distributed under the License is distributed on an "AS IS" BASIS,
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; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; See the License for the specific language governing permissions and
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; limitations under the License.
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[BITS 64]
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extern cpu_exception
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SECTION .bss
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__amd64_registers:
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resb 8*24
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%macro CPU_EXCEPT 1
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global __cpu_except_%1:function
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__cpu_except_%1:
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call save_cpu_regs
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;; new stack frame
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push rbp
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mov rbp, rsp
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;; enter panic
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mov rdi, __amd64_registers
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mov rsi, %1
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mov rdx, 0
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call cpu_exception
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%endmacro
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%macro CPU_EXCEPT_CODE 1
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global __cpu_except_%1:function
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__cpu_except_%1:
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call save_cpu_regs
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;; pop error code
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pop rdx
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;; new stack frame
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push rbp
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mov rbp, rsp
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;; enter panic
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mov rdi, __amd64_registers
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mov rsi, %1
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call cpu_exception
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%endmacro
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SECTION .text
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%define regs(r) [__amd64_registers + r]
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save_cpu_regs:
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mov regs( 0), rax
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mov regs( 8), rbx
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mov regs(16), rcx
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mov regs(24), rdx
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mov regs(32), rbp
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mov regs(40), r8
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mov regs(48), r9
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mov regs(56), r10
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mov regs(64), r11
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mov regs(72), r12
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mov regs(80), r13
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mov regs(88), r14
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mov regs(96), r15
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mov rax, QWORD [rsp + 32]
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mov regs(104), rax
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mov regs(112), rsi
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mov regs(120), rdi
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mov rax, QWORD [rsp + 8]
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mov regs(128), rax
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pushf
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pop QWORD regs(136)
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mov rax, cr0
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mov regs(144), rax
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mov QWORD regs(152), 0
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mov rbx, cr2
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mov regs(160), rbx
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mov rcx, cr3
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mov regs(168), rcx
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mov rdx, cr4
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mov regs(176), rdx
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mov rax, cr8
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mov regs(184), rax
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ret
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CPU_EXCEPT 0
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CPU_EXCEPT 1
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CPU_EXCEPT 2
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CPU_EXCEPT 3
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CPU_EXCEPT 4
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CPU_EXCEPT 5
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CPU_EXCEPT 6
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CPU_EXCEPT 7
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CPU_EXCEPT_CODE 8
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CPU_EXCEPT 9
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CPU_EXCEPT_CODE 10
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CPU_EXCEPT_CODE 11
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CPU_EXCEPT_CODE 12
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CPU_EXCEPT_CODE 13
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CPU_EXCEPT_CODE 14
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CPU_EXCEPT 15
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CPU_EXCEPT 16
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CPU_EXCEPT_CODE 17
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CPU_EXCEPT 18
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CPU_EXCEPT 19
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CPU_EXCEPT 20
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CPU_EXCEPT_CODE 30

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