x86_64: Initial SMP support (WIP)

Author: fwsGonzo

api/kernel/irq_manager.hpp

@@ -123,7 +123,7 @@ class alignas(SMP_ALIGN) IRQ_manager {
   { return count_handled; }
 
   /** Initialize for a local APIC */
-  static void init(int cpuid);
+  static void init();
   IRQ_manager() = default;
 
 private:

src/arch/x86_64/CMakeLists.txt

@@ -3,6 +3,7 @@ set(CMAKE_ASM_NASM_OBJECT_FORMAT elf64)
 ### x86_64 arch specific ###
 set(ARCH_OBJECTS
   apic_asm.asm
+  apic_longmode.asm
   arch_start.asm
   interrupts.asm
   fiber_asm.asm

src/arch/x86_64/apic_longmode.asm

@@ -0,0 +1,73 @@
+; This file is a part of the IncludeOS unikernel - www.includeos.org
+;
+; Copyright 2015 Oslo and Akershus University College of Applied Sciences
+; and Alfred Bratterud
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+;     http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+;
+global __apic_trampoline:function
+extern __gdt64_base_pointer
+extern revenant_main
+
+%define P4_TAB    0x1000
+
+[BITS 32]
+__apic_trampoline:
+    pop edi  ;; cpuid
+
+    ;; use same pagetable as CPU 0
+    mov eax, P4_TAB
+    mov cr3, eax
+
+    ;; enable PAE
+    mov eax, cr4
+    or  eax, 1 << 5
+    mov cr4, eax
+
+    ;; enable long mode
+    mov ecx, 0xC0000080          ; EFER MSR
+    rdmsr
+    or  eax, 1 << 8              ; Long Mode bit
+    wrmsr
+
+    ;; enable paging
+    mov eax, cr0                 ; Set the A-register to control register 0.
+    or  eax, 1 << 31
+    mov cr0, eax                 ; Set control register 0 to the A-register.
+
+    ;; load 64-bit GDT
+    lgdt [__gdt64_base_pointer]
+    jmp  0x8:long_mode ;; 0x8 = code seg
+
+[BITS 64]
+long_mode:
+    ;; segment regs
+    mov cx, 0x10 ;; 0x10 = data seg
+    mov ds, cx
+    mov es, cx
+    mov fs, cx
+    mov gs, cx
+    mov ss, cx
+
+    ;; align stack
+    and  rsp, -16
+    ;; retrieve CPU id
+    mov rax, 1
+    cpuid
+    shr rbx, 24
+    ;; geronimo!
+    mov rdi, rbx
+    call revenant_main
+    ; stop execution
+    cli
+    hlt

src/arch/x86_64/arch_start.asm

@@ -15,6 +15,7 @@
 ; See the License for the specific language governing permissions and
 ; limitations under the License.
 global __arch_start:function
+global __gdt64_base_pointer
 extern kernel_start
 extern __multiboot_magic
 extern __multiboot_addr
@@ -78,19 +79,16 @@ __arch_start:
     ;; enable long mode
     mov ecx, 0xC0000080          ; EFER MSR
     rdmsr
-    or eax, 1 << 8               ; Long Mode bit
+    or  eax, 1 << 8              ; Long Mode bit
     wrmsr
 
     ;; enable paging
     mov eax, cr0                 ; Set the A-register to control register 0.
-    or eax, 1 << 31
+    or  eax, 1 << 31
     mov cr0, eax                 ; Set control register 0 to the A-register.
 
-    mov eax, DWORD[__multiboot_magic]        ; Preserve multiboot regs
-    mov ebx, DWORD[__multiboot_addr]
-
     ;; load 64-bit GDT
-    lgdt [GDT64.Pointer]
+    lgdt [__gdt64_base_pointer]
     jmp  GDT64.Code:long_mode
 
 
@@ -112,7 +110,7 @@ GDT64:
     db 00000000b                 ; Granularity.
     db 0                         ; Base (high).
     dw 0x0 ;; alignment padding
-  .Pointer:                    ; The GDT-pointer.
+__gdt64_base_pointer:
     dw $ - GDT64 - 1             ; Limit.
     dq GDT64                     ; Base.
 
@@ -130,12 +128,12 @@ long_mode:
 
     ;; set up new stack for 64-bit
     push rsp
-    mov rsp, STACK_LOCATION
-    mov rbp, rsp
+    mov  rsp, STACK_LOCATION
+    mov  rbp, rsp
 
     ;; geronimo!
-    mov rdi, rax
-    mov rsi, rbx
+    mov  edi, DWORD[__multiboot_magic]
+    mov  esi, DWORD[__multiboot_addr]
     call kernel_start
     pop  rsp
     ret

src/kernel/irq_manager.cpp

@@ -218,9 +218,9 @@ void IRQ_manager::enable_interrupts() {
   asm volatile("sti");
 }
 
-void IRQ_manager::init(int cpuid)
+void IRQ_manager::init()
 {
-  get(cpuid).init_local();
+  get().init_local();
 }
 
 void IRQ_manager::init_local()
@@ -359,9 +359,10 @@ void IRQ_manager::subscribe(uint8_t irq, irq_delegate del)
   irq_subs.atomic_set(irq);
 
   // Create stat for this event
-  Stat& subscribed = Statman::get().create(Stat::UINT64,
-      "cpu" + std::to_string(SMP::cpu_id()) + ".irq" + std::to_string(irq));
-  count_handled[irq] = &subscribed.get_uint64();
+  //Stat& subscribed = Statman::get().create(Stat::UINT64,
+  //    "cpu" + std::to_string(SMP::cpu_id()) + ".irq" + std::to_string(irq));
+  //count_handled[irq] = &subscribed.get_uint64();
+  count_handled[irq] = nullptr;
 
   // Add callback to subscriber list (for now overwriting any previous)
   irq_delegates_[irq] = del;

src/platform/x86_pc/apic_boot.asm

@@ -34,19 +34,19 @@ ALIGN 4
 boot_code:
   ; disable interrupts
   cli
-  
+
   ; segment descriptor table
   lgdt  [cs:gdtr]
-  
+
   mov   edx, cr0  ; set bit 0 of CR0
   or    edx, 1    ; to enable protected mode
   mov   cr0, edx
-  
+
   ; A small delay
   nop
   nop
   nop
-  
+
   ; flush and enter protected mode
   JMP DWORD 0x08:protected_mode
 
@@ -56,7 +56,7 @@ gdtr:
   dq gdt32
 gdt32:
   ;; Entry 0x0: Null desriptor
-  dq 0x0 
+  dq 0x0
   ;; Entry 0x8: Code segment
   dw 0xffff          ;Limit
   dw 0x0000          ;Base 15:00
@@ -68,38 +68,36 @@ gdt32:
   dw 0x0000          ;Base 15:00
   db 0x00            ;Base 23:16
   dw 0xcf92          ;Flags
-  db 0x00            ;Base 32:24  
+  db 0x00            ;Base 32:24
 gdt32_end:
 
 BITS 32
 protected_mode:
   cld
-  
+
   ; set most segments to data (0x10)
   mov   ax, 0x10
   mov   ds, ax
   mov   es, ax
   mov   ss, ax
-  
+
   ; retrieve CPU id
   mov eax, 1
   cpuid
   shr ebx, 24
-  
+
   ; give separate stack to each cpu
   mov eax, DWORD [stack_size]
   mul ebx
   add eax, [stack_base]
   mov ebp, eax
   mov esp, ebp
-  
+
   ; enable SSE
   call enable_sse
-  
+
   push  ebx
   call  [revenant_main]
-  pop   ebx
-  
   ; stop execution
   cli
   hlt

src/platform/x86_pc/apic_revenant.cpp

@@ -2,7 +2,6 @@
 
 #include "apic.hpp"
 #include "apic_timer.hpp"
-#include "gdt.hpp"
 #include <kernel/irq_manager.hpp>
 #include <kprint>
 
@@ -64,13 +63,13 @@ void revenant_main(int cpu)
   x86::APIC::get().smp_enable();
   // setup GDT & per-cpu feature
   initialize_gdt_for_cpu(cpu);
-  // newlibs printf just does way too much static stuff to work in SMP
-  // it can work if REENTs are initalized per-cpu ... and other things
+  // show we are online, and verify CPU ID is correct
   ::SMP::global_lock();
-  INFO2("AP %d started at %p", get_cpu_id(), get_cpu_esp());
+  INFO2("AP %d started at %p", cpu, get_cpu_esp());
   ::SMP::global_unlock();
+  assert(cpu == ::SMP::cpu_id());
 
-  IRQ_manager::init(cpu);
+  IRQ_manager::init();
   // enable interrupts
   IRQ_manager::enable_interrupts();
   // init timer system

src/platform/x86_pc/apic_revenant.hpp

@@ -23,25 +23,24 @@
 #include <cstdint>
 #include <deque>
 
-extern "C"
-void revenant_main(int);
+extern "C" void revenant_main(int);
 
 struct smp_stuff
 {
   struct task {
     task(SMP::task_func a,
          SMP::done_func b)
       : func(a), done(b) {}
-    
+
     SMP::task_func func;
     SMP::done_func done;
   };
-  
+
   minimal_barrier_t boot_barrier;
-  
+
   spinlock_t tlock;
   std::deque<task> tasks;
-  
+
   spinlock_t flock;
   std::deque<SMP::done_func> completed;
 };

src/platform/x86_pc/platform.cpp

@@ -50,7 +50,7 @@ void __platform_init()
   initialize_gdt_for_cpu(APIC::get().get_id());
 
   // IDT manager: Interrupt and exception handlers
-  IRQ_manager::init(APIC::get().get_id());
+  IRQ_manager::init();
 
   // initialize and start registered APs found in ACPI-tables
 #ifndef INCLUDEOS_SINGLE_THREADED

src/platform/x86_pc/smp.cpp

@@ -28,26 +28,27 @@
 extern "C" {
   extern char _binary_apic_boot_bin_start;
   extern char _binary_apic_boot_bin_end;
+  extern void __apic_trampoline(); // 64-bit entry
 }
 
 static const uintptr_t BOOTLOADER_LOCATION = 0x10000;
 static const size_t    REV_STACK_SIZE = 1 << 18; // 256kb
 
 struct apic_boot {
   // the jump instruction at the start
-  uint32_t  jump;
+  uint32_t  padding;
   // stuff we will modify
-  void*     worker_addr;
-  char*     stack_base;
-  size_t    stack_size;
+  uint32_t  worker_addr;
+  uint32_t  stack_base;
+  uint32_t  stack_size;
 };
 
 namespace x86
 {
 
 void SMP::init()
 {
-  size_t CPUcount = ACPI::get_cpus().size();
+  uint32_t CPUcount = ACPI::get_cpus().size();
   if (CPUcount <= 1) return;
   assert(CPUcount <= SMP_MAX_CORES);
 
@@ -59,11 +60,18 @@ void SMP::init()
   // modify bootloader to support our cause
   auto* boot = (apic_boot*) BOOTLOADER_LOCATION;
 
-  boot->worker_addr = (void*) &revenant_main;
-  boot->stack_base = (char*) memalign(4096, CPUcount * REV_STACK_SIZE);
+#if defined(ARCH_i686)
+  boot->worker_addr = (uint32_t) &revenant_main;
+#elif defined(ARCH_x86_64)
+  boot->worker_addr = (uint32_t) (uintptr_t) &__apic_trampoline;
+#else
+  #error "Unimplemented arch"
+#endif
+  auto* stack = memalign(4096, CPUcount * REV_STACK_SIZE);
+  boot->stack_base = (uint32_t) (uintptr_t) stack;
   boot->stack_base += REV_STACK_SIZE; // make sure the stack starts at the top
   boot->stack_size = REV_STACK_SIZE;
-  debug("APIC stack base: %p  size: %u   main size: %u\n",
+  debug("APIC stack base: %#x  size: %u   main size: %u\n",
       boot->stack_base, boot->stack_size, sizeof(boot->worker_addr));
 
   // reset barrier