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amd64: move processor control structures to snapshot region
This commit changes the code that sets up all these processor control structures to allocate pages from the scratch region, map them to an arbitrary VA, and then point the processor at that VA (in order to ensure that they survive snapshotting at the same VA). It also refactors the architecture-specific initialisation code somewhat, in order to make it a bit easier to have one memory allocation shared by all the relevant tables & in preparation for future multi-architecture support. Signed-off-by: Lucy Menon <168595099+syntactically@users.noreply.github.com>
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22 files changed

Lines changed: 849 additions & 741 deletions

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‎src/hyperlight_common/src/arch/amd64/layout.rs‎

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@@ -14,6 +14,10 @@ See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// The addresses in this file should be coordinated with
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// src/hyperlight_guest/src/arch/amd64/layout.rs and
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// src/hyperlight_guest_bin/src/arch/amd64/layout.rs
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/// We have this the top of the page below the top of memory in order
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/// to make working with start/end ptrs in a few places more
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/// convenient (not needing to worry about overflow)

‎src/hyperlight_guest/src/arch/amd64/layout.rs‎

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@@ -14,7 +14,11 @@ See the License for the specific language governing permissions and
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limitations under the License.
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*/
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pub const MAIN_STACK_TOP_GVA: usize = 0xffff_feff_ffff_f000;
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// The addresses in this file should be coordinated with
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// src/hyperlight_common/src/arch/amd64/layout.rs and
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// src/hyperlight_guest_bin/src/arch/amd64/layout.rs
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pub const MAIN_STACK_TOP_GVA: u64 = 0xffff_feff_ffff_f000;
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pub fn scratch_size() -> u64 {
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let addr = crate::layout::scratch_size_gva();

‎src/hyperlight_guest_bin/src/arch/amd64/context.rs‎

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/*
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Copyright 2025 The Hyperlight Authors.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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use super::machine::ExceptionInfo;
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#[repr(C)]
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/// Saved context, pushed onto the stack by exception entry code
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pub struct Context {
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/// in order: ds, gs, fs, es
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pub segments: [u64; 4],
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pub fxsave: [u8; 512],
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/// no `rsp`, since the processor saved it
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/// `rax` is at the top, `r15` the bottom
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pub gprs: [u64; 15],
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_padding: u64,
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}
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const _: () = assert!(size_of::<Context>() == 32 + 512 + 120 + 8);
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// The combination of the ExceptionInfo (pushed by the CPU) and the
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// register Context that we save to the stack must be 16byte aligned
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// before calling the hl_exception_handler as specified in the x86-64
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// ELF System V psABI specification, Section 3.2.2:
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//
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// https://gitlab.com/x86-psABIs/x86-64-ABI/-/jobs/artifacts/master/raw/x86-64-ABI/abi.pdf?job=build
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const _: () = assert!((size_of::<Context>() + size_of::<ExceptionInfo>()).is_multiple_of(16));
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// Defines `context_save` and `context_restore`
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macro_rules! save {
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() => {
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concat!(
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// Save general-purpose registers
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" sub rsp, 8\n",
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" push rax\n",
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" push rbx\n",
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" push rcx\n",
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" push rdx\n",
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" push rsi\n",
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" push rdi\n",
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" push rbp\n",
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" push r8\n",
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" push r9\n",
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" push r10\n",
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" push r11\n",
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" push r12\n",
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" push r13\n",
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" push r14\n",
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" push r15\n",
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// Save floating-point/SSE registers
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// TODO: Don't do this unconditionally: get the exn
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// handlers compiled without sse
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// TODO: Check if we ever generate code with ymm/zmm in
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// the handlers and save/restore those as well
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" sub rsp, 512\n",
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" mov rax, rsp\n",
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" fxsave [rax]\n",
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// Save the rest of the segment registers
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" mov rax, es\n",
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" push rax\n",
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" mov rax, fs\n",
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" push rax\n",
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" mov rax, gs\n",
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" push rax\n",
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" mov rax, ds\n",
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" push rax\n",
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)
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};
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}
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pub(super) use save;
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macro_rules! restore {
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() => {
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concat!(
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// Restore most segment registers
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" pop rax\n",
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" mov ds, rax\n",
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" pop rax\n",
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" mov gs, rax\n",
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" pop rax\n",
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" mov fs, rax\n",
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" pop rax\n",
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" mov es, rax\n",
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// Restore floating-point/SSE registers
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" mov rax, rsp\n",
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" fxrstor [rax]\n",
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" add rsp, 512\n",
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// Restore general-purpose registers
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" pop r15\n",
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" pop r14\n",
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" pop r13\n",
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" pop r12\n",
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" pop r11\n",
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" pop r10\n",
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" pop r9\n",
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" pop r8\n",
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" pop rbp\n",
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" pop rdi\n",
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" pop rsi\n",
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" pop rdx\n",
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" pop rcx\n",
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" pop rbx\n",
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" pop rax\n",
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" add rsp, 8\n",
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)
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};
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}
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pub(super) use restore;

‎src/hyperlight_guest_bin/src/arch/amd64/exception/entry.rs‎

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/*
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Copyright 2025 The Hyperlight Authors.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// Note: this code takes reference from
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// https://github.com/nanvix/nanvix/blob/dev/src/kernel/src/hal/arch/x86/hooks.S
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use core::arch::{asm, global_asm};
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use hyperlight_common::outb::Exception;
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use super::super::context;
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use super::super::machine::{IDT, IdtEntry, IdtPointer, ProcCtrl};
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unsafe extern "C" {
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// Exception handlers
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fn _do_excp0();
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fn _do_excp1();
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fn _do_excp2();
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fn _do_excp3();
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fn _do_excp4();
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fn _do_excp5();
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fn _do_excp6();
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fn _do_excp7();
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fn _do_excp8();
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fn _do_excp9();
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fn _do_excp10();
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fn _do_excp11();
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fn _do_excp12();
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fn _do_excp13();
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fn _do_excp14();
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fn _do_excp15();
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fn _do_excp16();
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fn _do_excp17();
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fn _do_excp18();
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fn _do_excp19();
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fn _do_excp20();
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fn _do_excp30();
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}
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// Macro to generate exception handlers
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// that satisfy the `extern`s at the top of the file.
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//
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// - Example output from this macro for generate_excp!(0) call:
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// ```assembly
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// .global _do_excp0
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// _do_excp0:
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// context_save!()
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// mov rsi, 0
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// mov rdx, 0
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// jmp _do_excp_common
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// ```
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macro_rules! generate_excp {
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($num:expr) => {
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concat!(
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".global _do_excp",
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stringify!($num),
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"\n",
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"_do_excp",
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stringify!($num),
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":\n",
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context::save!(),
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// rsi is the exception number.
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" mov rsi, ",
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stringify!($num),
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"\n",
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// rdx is only used for pagefault exception and
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// contains the address that caused the pagefault.
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" mov rdx, 0\n",
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" jmp _do_excp_common\n"
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)
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};
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($num:expr, pusherrcode) => {
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concat!(
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".global _do_excp",
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stringify!($num),
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"\n",
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"_do_excp",
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stringify!($num),
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":\n",
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// Some exceptions push an error code onto the stack.
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// For the ones that don't, we push a 0 to keep the
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// stack aligned.
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" push 0\n",
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context::save!(),
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// rsi is the exception number.
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" mov rsi, ",
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stringify!($num),
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"\n",
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// rdx is only used for pagefault exception and
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// contains the address that caused the pagefault.
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" mov rdx, 0\n",
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" jmp _do_excp_common\n"
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)
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};
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($num:expr, pagefault) => {
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concat!(
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".global _do_excp",
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stringify!($num),
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"\n",
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"_do_excp",
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stringify!($num),
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":\n",
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context::save!(),
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" mov rsi, ",
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stringify!($num),
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"\n",
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// In a page fault exception, the cr2 register
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// contains the address that caused the page fault.
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" mov rdx, cr2\n",
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" jmp _do_excp_common\n"
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)
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};
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}
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// Generates exception handlers
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macro_rules! generate_exceptions {
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() => {
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concat!(
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// Common exception handler
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".global _do_excp_common\n",
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"_do_excp_common:\n",
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// the first argument to the Rust handler points to the
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// bottom of the context struct, which happens to be the
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// stack pointer just before it was called.
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" mov rdi, rsp\n",
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" call {hl_exception_handler}\n",
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context::restore!(),
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" add rsp, 8\n", // error code
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" iretq\n", // iretq is used to return from exception in x86_64
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generate_excp!(0, pusherrcode),
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generate_excp!(1, pusherrcode),
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generate_excp!(2, pusherrcode),
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generate_excp!(3, pusherrcode),
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generate_excp!(4, pusherrcode),
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generate_excp!(5, pusherrcode),
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generate_excp!(6, pusherrcode),
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generate_excp!(7, pusherrcode),
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generate_excp!(8),
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generate_excp!(9, pusherrcode),
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generate_excp!(10),
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generate_excp!(11),
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generate_excp!(12),
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generate_excp!(13),
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generate_excp!(14, pagefault),
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generate_excp!(15, pusherrcode),
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generate_excp!(16, pusherrcode),
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generate_excp!(17),
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generate_excp!(18, pusherrcode),
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generate_excp!(19, pusherrcode),
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generate_excp!(20, pusherrcode),
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generate_excp!(30),
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)
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};
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}
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// Output the assembly code
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global_asm!(
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generate_exceptions!(),
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hl_exception_handler = sym super::handle::hl_exception_handler,
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);
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pub(in super::super) fn init_idt(pc: *mut ProcCtrl) {
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let idt = unsafe { &raw mut (*pc).idt };
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let set_idt_entry = |idx, handler: unsafe extern "C" fn()| {
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let handler_addr = handler as *const () as u64;
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unsafe {
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(&raw mut (*idt).entries[idx as usize]).write_volatile(IdtEntry::new(handler_addr));
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}
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};
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set_idt_entry(Exception::DivideByZero, _do_excp0); // Divide by zero
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set_idt_entry(Exception::Debug, _do_excp1); // Debug
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set_idt_entry(Exception::NonMaskableInterrupt, _do_excp2); // Non-maskable interrupt
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set_idt_entry(Exception::Breakpoint, _do_excp3); // Breakpoint
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set_idt_entry(Exception::Overflow, _do_excp4); // Overflow
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set_idt_entry(Exception::BoundRangeExceeded, _do_excp5); // Bound Range Exceeded
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set_idt_entry(Exception::InvalidOpcode, _do_excp6); // Invalid Opcode
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set_idt_entry(Exception::DeviceNotAvailable, _do_excp7); // Device Not Available
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set_idt_entry(Exception::DoubleFault, _do_excp8); // Double Fault
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set_idt_entry(Exception::CoprocessorSegmentOverrun, _do_excp9); // Coprocessor Segment Overrun
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set_idt_entry(Exception::InvalidTSS, _do_excp10); // Invalid TSS
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set_idt_entry(Exception::SegmentNotPresent, _do_excp11); // Segment Not Present
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set_idt_entry(Exception::StackSegmentFault, _do_excp12); // Stack-Segment Fault
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set_idt_entry(Exception::GeneralProtectionFault, _do_excp13); // General Protection Fault
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set_idt_entry(Exception::PageFault, _do_excp14); // Page Fault
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set_idt_entry(Exception::Reserved, _do_excp15); // Reserved
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set_idt_entry(Exception::X87FloatingPointException, _do_excp16); // x87 Floating-Point Exception
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set_idt_entry(Exception::AlignmentCheck, _do_excp17); // Alignment Check
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set_idt_entry(Exception::MachineCheck, _do_excp18); // Machine Check
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set_idt_entry(Exception::SIMDFloatingPointException, _do_excp19); // SIMD Floating-Point Exception
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set_idt_entry(Exception::VirtualizationException, _do_excp20); // Virtualization Exception
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set_idt_entry(Exception::SecurityException, _do_excp30); // Security Exception
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let idtr = IdtPointer {
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limit: (core::mem::size_of::<IDT>() - 1) as u16,
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base: idt as u64,
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};
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unsafe {
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asm!(
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"lidt [{}]",
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in(reg) &idtr,
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options(readonly, nostack, preserves_flags)
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);
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}
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}

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