Stock-Ticker-Hardware/Stock-Ticker-Hardware.kicad_dru at main · UnsignedArduino/Stock-Ticker-Hardware · GitHub

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(version 1)
# Custom Design Rules (DRC) for KiCAD 8.0 (2 Layers PCB) (Stored in '<project>.kicad_dru' file).
#
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
#
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
#
# Last revision: 2025-01-04

(rule "Minimum Track Width"
	(condition "A.Type == 'track'")
	(constraint track_width (min 0.10mm))
)

(rule "Minimum Track Clearance"
	(condition "A.Type == 'track' && B.Type == A.Type")
	(constraint clearance (min 0.10mm))
)

# silkscreen
(rule "Minimum Silkscreen Text Size"
	(layer "?.Silkscreen")
	(condition "A.Type == 'Text' || A.Type == 'Text Box'")
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
)

(rule "Pad to Silkscreen Clearance"
	(layer outer)
	(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
	(constraint silk_clearance (min 0.15mm))
)

# edge clearance
(rule "Track to Board Edge Clearance"
	(condition "A.Type == 'track'")
	(constraint edge_clearance (min 0.2mm))
)

# drill/hole size
(rule "Mechanical Drill Hole Size"
	(constraint hole_size (min 0.15mm) (max 6.3mm))
)

(rule "Minimum Via Hole Size"
	(condition "A.Type == 'via'")
	(constraint hole_size (min 0.15mm))
)

(rule "Minimum Via Diameter"
	(condition "A.Type == 'via'")
	(constraint via_diameter (min 0.25mm))
)

(rule "PTH Hole Size"
	(condition "A.isPlated()")
	(constraint hole_size (min 0.15mm) (max 6.35mm))
)

(rule "NPTH Hole Size"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint hole_size (min 0.5mm))
)

(rule "Castellated Hole Size"
	(layer outer)
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
	(constraint hole_size (min 0.6mm))
)

(rule "Annular Ring Width (PTH)"
	(layer outer)
	(condition "A.isPlated()")
	(constraint annular_width (min 0.20mm))
)

(rule "Annular Ring Width (NPTH)"
	(layer outer)
	(condition "!A.isPlated()")
	(constraint annular_width (min 0.45mm))
)

# clearance
(rule "Hole to Hole Clearance (diff. nets)"
	(layer outer)
	(condition "A.Net != B.Net")
	(constraint hole_to_hole (min 0.45mm))
)

(rule "Hole to Hole Clearance (same net)"
	(layer outer)
	(condition "A.Net == B.Net")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Via to Track Clearance"
	(condition "A.Type == 'via' && B.Type == 'track'")
	(constraint hole_clearance (min 0.2mm))
)

(rule "Via to Via Clearance (same net)"
	(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")
	(constraint hole_to_hole (min 0.2mm))
)

(rule "Pad to Pad Clearance (with hole, diff. nets)"
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")
	(constraint hole_to_hole (min 0.45mm))
)

(rule "Pad to Pad Clearance (without hole, diff. nets)"
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")
	(constraint clearance (min 0.127mm))
)

(rule "NPTH to Track Clearance"
	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")
	(constraint hole_clearance (min 0.2mm))
)

(rule "PTH to Track Clearance"
	(condition "A.isPlated() && B.Type == 'track'")
	(constraint hole_clearance (min 0.28mm))
)

(rule "Pad to Track Clearance"
	(condition "A.isPlated() && B.Type == 'track'")
	(constraint clearance (min 0.1mm))
)

# additional rules
(rule "Copper to Board Edge Clearance"
	(condition "A.Type == 'track' || A.Type == 'zone'")
	(constraint edge_clearance (min 0.2mm))
)

(rule "Copper Pour to Copper Pour Clearance"
	(condition "A.Type == 'zone'")
	(constraint clearance (min 0.2mm))
)

(rule "Blind/Buried Vias (Not Supported)"
	(condition "A.Type == 'via' && A.Layer != 'outer'")
	(constraint hole_size (min 0.15mm))
)