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drm/i915: use direct alias for i915 in requests
i915_request contains direct alias to i915, there is no point to go via rq->engine->i915. v2: added missing rq.i915 initialization in measure_breadcrumb_dw. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230720113002.1541572-1-andrzej.hajda@intel.com
1 parent e4731b5 commit d3f23ab

18 files changed

Lines changed: 43 additions & 42 deletions

‎drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2230,8 +2230,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
22302230
u32 *cs;
22312231
int i;
22322232

2233-
if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
2234-
drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
2233+
if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
2234+
drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
22352235
return -EINVAL;
22362236
}
22372237

‎drivers/gpu/drm/i915/gt/gen2_engine_cs.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
7676
cmd = MI_FLUSH;
7777
if (mode & EMIT_INVALIDATE) {
7878
cmd |= MI_EXE_FLUSH;
79-
if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
79+
if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
8080
cmd |= MI_INVALIDATE_ISP;
8181
}
8282

‎drivers/gpu/drm/i915/gt/gen8_engine_cs.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
3939
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
4040
* pipe control.
4141
*/
42-
if (GRAPHICS_VER(rq->engine->i915) == 9)
42+
if (GRAPHICS_VER(rq->i915) == 9)
4343
vf_flush_wa = true;
4444

4545
/* WaForGAMHang:kbl */
46-
if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
46+
if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
4747
dc_flush_wa = true;
4848
}
4949

@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
180180
static int mtl_dummy_pipe_control(struct i915_request *rq)
181181
{
182182
/* Wa_14016712196 */
183-
if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
184-
IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
183+
if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
184+
IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
185185
u32 *cs;
186186

187187
/* dummy PIPE_CONTROL + depth flush */
@@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
267267
else if (engine->class == COMPUTE_CLASS)
268268
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
269269

270-
if (!HAS_FLAT_CCS(rq->engine->i915))
270+
if (!HAS_FLAT_CCS(rq->i915))
271271
count = 8 + 4;
272272
else
273273
count = 8;
@@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
285285

286286
cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
287287

288-
if (!HAS_FLAT_CCS(rq->engine->i915)) {
288+
if (!HAS_FLAT_CCS(rq->i915)) {
289289
/* hsdes: 1809175790 */
290290
cs = gen12_emit_aux_table_inv(rq->engine->gt,
291291
cs, GEN12_GFX_CCS_AUX_NV);
@@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
307307
if (mode & EMIT_INVALIDATE) {
308308
cmd += 2;
309309

310-
if (!HAS_FLAT_CCS(rq->engine->i915) &&
310+
if (!HAS_FLAT_CCS(rq->i915) &&
311311
(rq->engine->class == VIDEO_DECODE_CLASS ||
312312
rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
313313
aux_inv = rq->engine->mask &
@@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
754754

755755
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
756756
{
757-
struct drm_i915_private *i915 = rq->engine->i915;
757+
struct drm_i915_private *i915 = rq->i915;
758758
u32 flags = (PIPE_CONTROL_CS_STALL |
759759
PIPE_CONTROL_TLB_INVALIDATE |
760760
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
775775
/* Wa_1409600907 */
776776
flags |= PIPE_CONTROL_DEPTH_STALL;
777777

778-
if (!HAS_3D_PIPELINE(rq->engine->i915))
778+
if (!HAS_3D_PIPELINE(rq->i915))
779779
flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
780780
else if (rq->engine->class == COMPUTE_CLASS)
781781
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;

‎drivers/gpu/drm/i915/gt/intel_engine_cs.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1333,6 +1333,7 @@ static int measure_breadcrumb_dw(struct intel_context *ce)
13331333
if (!frame)
13341334
return -ENOMEM;
13351335

1336+
frame->rq.i915 = engine->i915;
13361337
frame->rq.engine = engine;
13371338
frame->rq.context = ce;
13381339
rcu_assign_pointer(frame->rq.timeline, ce->timeline);

‎drivers/gpu/drm/i915/gt/intel_execlists_submission.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2717,7 +2717,7 @@ static int emit_pdps(struct i915_request *rq)
27172717
int err, i;
27182718
u32 *cs;
27192719

2720-
GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
2720+
GEM_BUG_ON(intel_vgpu_active(rq->i915));
27212721

27222722
/*
27232723
* Beware ye of the dragons, this sequence is magic!

‎drivers/gpu/drm/i915/gt/intel_migrate.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
366366
u64 offset,
367367
int length)
368368
{
369-
bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
369+
bool has_64K_pages = HAS_64K_PAGES(rq->i915);
370370
const u64 encode = rq->context->vm->pte_encode(0, pat_index,
371371
is_lmem ? PTE_LM : 0);
372372
struct intel_ring *ring = rq->ring;
@@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
375375
u32 page_size;
376376
u32 *hdr, *cs;
377377

378-
GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
378+
GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
379379

380380
page_size = I915_GTT_PAGE_SIZE;
381381
dword_length = 0x400;
@@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
531531
u32 dst_offset, u8 dst_access,
532532
u32 src_offset, u8 src_access, int size)
533533
{
534-
struct drm_i915_private *i915 = rq->engine->i915;
534+
struct drm_i915_private *i915 = rq->i915;
535535
int mocs = rq->engine->gt->mocs.uc_index << 1;
536536
u32 num_ccs_blks;
537537
u32 *cs;
@@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
581581
static int emit_copy(struct i915_request *rq,
582582
u32 dst_offset, u32 src_offset, int size)
583583
{
584-
const int ver = GRAPHICS_VER(rq->engine->i915);
584+
const int ver = GRAPHICS_VER(rq->i915);
585585
u32 instance = rq->engine->instance;
586586
u32 *cs;
587587

@@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context *ce,
917917
static int emit_clear(struct i915_request *rq, u32 offset, int size,
918918
u32 value, bool is_lmem)
919919
{
920-
struct drm_i915_private *i915 = rq->engine->i915;
920+
struct drm_i915_private *i915 = rq->i915;
921921
int mocs = rq->engine->gt->mocs.uc_index << 1;
922922
const int ver = GRAPHICS_VER(i915);
923923
int ring_sz;

‎drivers/gpu/drm/i915/gt/intel_ring_submission.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
805805
static int remap_l3_slice(struct i915_request *rq, int slice)
806806
{
807807
#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
808-
u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
808+
u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
809809
int i;
810810

811811
if (!remap_info)

‎drivers/gpu/drm/i915/gt/intel_workarounds.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
32493249
const struct i915_wa_list *wal,
32503250
struct i915_vma *vma)
32513251
{
3252-
struct drm_i915_private *i915 = rq->engine->i915;
3252+
struct drm_i915_private *i915 = rq->i915;
32533253
unsigned int i, count = 0;
32543254
const struct i915_wa *wa;
32553255
u32 srm, *cs;
@@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
33483348

33493349
err = 0;
33503350
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3351-
if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
3351+
if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
33523352
continue;
33533353

33543354
if (!wa_verify(wal->gt, wa, results[i], wal->name, from))

‎drivers/gpu/drm/i915/gt/selftest_engine_cs.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
6262
return PTR_ERR(cs);
6363

6464
cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
65-
if (GRAPHICS_VER(rq->engine->i915) >= 8)
65+
if (GRAPHICS_VER(rq->i915) >= 8)
6666
cmd++;
6767
*cs++ = cmd;
6868
*cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));

‎drivers/gpu/drm/i915/gt/selftest_mocs.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
137137
if (!table)
138138
return 0;
139139

140-
if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
140+
if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
141141
addr = global_mocs_offset() + gt->uncore->gsi_offset;
142142
else
143143
addr = mocs_offset(rq->engine);

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