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RISC-V: KVM: Sort ISA extensions alphabetically in ONE_REG interface
Let us sort isa extensions alphabetically in kvm_isa_ext_arr[] and kvm_riscv_vcpu_isa_disable_allowed() so that future insertions are more predictable. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org>
1 parent 043cba0 commit d2064d4

1 file changed

Lines changed: 7 additions & 6 deletions

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arch/riscv/kvm/vcpu_onereg.c

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
2424

2525
/* Mapping between KVM ISA Extension ID & Host ISA extension ID */
2626
static const unsigned long kvm_isa_ext_arr[] = {
27+
/* Single letter extensions (alphabetically sorted) */
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[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
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[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
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[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
@@ -32,7 +33,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
3233
[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
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[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
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[KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
35-
36+
/* Multi letter extensions (alphabetically sorted) */
3637
KVM_ISA_EXT_ARR(SSAIA),
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KVM_ISA_EXT_ARR(SSTC),
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KVM_ISA_EXT_ARR(SVINVAL),
@@ -41,13 +42,13 @@ static const unsigned long kvm_isa_ext_arr[] = {
4142
KVM_ISA_EXT_ARR(ZBA),
4243
KVM_ISA_EXT_ARR(ZBB),
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KVM_ISA_EXT_ARR(ZBS),
45+
KVM_ISA_EXT_ARR(ZICBOM),
46+
KVM_ISA_EXT_ARR(ZICBOZ),
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KVM_ISA_EXT_ARR(ZICNTR),
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KVM_ISA_EXT_ARR(ZICSR),
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KVM_ISA_EXT_ARR(ZIFENCEI),
4750
KVM_ISA_EXT_ARR(ZIHINTPAUSE),
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KVM_ISA_EXT_ARR(ZIHPM),
49-
KVM_ISA_EXT_ARR(ZICBOM),
50-
KVM_ISA_EXT_ARR(ZICBOZ),
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};
5253

5354
static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -87,14 +88,14 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
8788
case KVM_RISCV_ISA_EXT_SSTC:
8889
case KVM_RISCV_ISA_EXT_SVINVAL:
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case KVM_RISCV_ISA_EXT_SVNAPOT:
91+
case KVM_RISCV_ISA_EXT_ZBA:
92+
case KVM_RISCV_ISA_EXT_ZBB:
93+
case KVM_RISCV_ISA_EXT_ZBS:
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case KVM_RISCV_ISA_EXT_ZICNTR:
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case KVM_RISCV_ISA_EXT_ZICSR:
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case KVM_RISCV_ISA_EXT_ZIFENCEI:
9397
case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
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case KVM_RISCV_ISA_EXT_ZIHPM:
95-
case KVM_RISCV_ISA_EXT_ZBA:
96-
case KVM_RISCV_ISA_EXT_ZBB:
97-
case KVM_RISCV_ISA_EXT_ZBS:
9899
return false;
99100
default:
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break;

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