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Merge tag 'imx-fixes-6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX fixes for 6.1, part 3: - Fix a small memory leak in mach-mxs code. - Correct PCIe pad configuration for imx8mp-evk board. - Fix ref/tcxo clock frequency property for imx6q-prti6q board. * tag 'imx-fixes-6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx6q-prti6q: Fix ref/tcxo-clock-frequency properties arm64: dts: imx8mp-evk: correct pcie pad settings ARM: mxs: fix memory leak in mxs_machine_init() Link: https://lore.kernel.org/r/20221119073812.GQ16229@T480 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents e7135a2 + e68be7b commit cafd3d3

3 files changed

Lines changed: 8 additions & 6 deletions

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arch/arm/boot/dts/imx6q-prti6q.dts

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -364,8 +364,8 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wifi>;
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interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
367-
ref-clock-frequency = "38400000";
368-
tcxo-clock-frequency = "19200000";
367+
ref-clock-frequency = <38400000>;
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tcxo-clock-frequency = <19200000>;
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};
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};
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arch/arm/mach-mxs/mach-mxs.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -393,8 +393,10 @@ static void __init mxs_machine_init(void)
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root = of_find_node_by_path("/");
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ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
396-
if (ret)
396+
if (ret) {
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kfree(soc_dev_attr);
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return;
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}
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soc_dev_attr->family = "Freescale MXS Family";
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soc_dev_attr->soc_id = mxs_get_soc_id();

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -544,14 +544,14 @@
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
547-
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
548-
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
547+
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
548+
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
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>;
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};
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pinctrl_pcie0_reg: pcie0reggrp {
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fsl,pins = <
554-
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
554+
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
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>;
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};
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