@@ -669,17 +669,13 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
669669{
670670 struct intel_gt * gt = rps_to_gt (rps );
671671 struct intel_uncore * uncore = gt -> uncore ;
672- u32 threshold_up = 0 , threshold_down = 0 ; /* in % */
673672 u32 ei_up = 0 , ei_down = 0 ;
674673
675674 lockdep_assert_held (& rps -> power .mutex );
676675
677676 if (new_power == rps -> power .mode )
678677 return ;
679678
680- threshold_up = 95 ;
681- threshold_down = 85 ;
682-
683679 /* Note the units here are not exactly 1us, but 1280ns. */
684680 switch (new_power ) {
685681 case LOW_POWER :
@@ -706,17 +702,22 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
706702
707703 GT_TRACE (gt ,
708704 "changing power mode [%d], up %d%% @ %dus, down %d%% @ %dus\n" ,
709- new_power , threshold_up , ei_up , threshold_down , ei_down );
705+ new_power ,
706+ rps -> power .up_threshold , ei_up ,
707+ rps -> power .down_threshold , ei_down );
710708
711709 set (uncore , GEN6_RP_UP_EI ,
712710 intel_gt_ns_to_pm_interval (gt , ei_up * 1000 ));
713711 set (uncore , GEN6_RP_UP_THRESHOLD ,
714- intel_gt_ns_to_pm_interval (gt , ei_up * threshold_up * 10 ));
712+ intel_gt_ns_to_pm_interval (gt ,
713+ ei_up * rps -> power .up_threshold * 10 ));
715714
716715 set (uncore , GEN6_RP_DOWN_EI ,
717716 intel_gt_ns_to_pm_interval (gt , ei_down * 1000 ));
718717 set (uncore , GEN6_RP_DOWN_THRESHOLD ,
719- intel_gt_ns_to_pm_interval (gt , ei_down * threshold_down * 10 ));
718+ intel_gt_ns_to_pm_interval (gt ,
719+ ei_down *
720+ rps -> power .down_threshold * 10 ));
720721
721722 set (uncore , GEN6_RP_CONTROL ,
722723 (GRAPHICS_VER (gt -> i915 ) > 9 ? 0 : GEN6_RP_MEDIA_TURBO ) |
@@ -728,8 +729,6 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
728729
729730skip_hw_write :
730731 rps -> power .mode = new_power ;
731- rps -> power .up_threshold = threshold_up ;
732- rps -> power .down_threshold = threshold_down ;
733732}
734733
735734static void gen6_rps_set_thresholds (struct intel_rps * rps , u8 val )
@@ -1555,10 +1554,12 @@ void intel_rps_enable(struct intel_rps *rps)
15551554 return ;
15561555
15571556 GT_TRACE (rps_to_gt (rps ),
1558- "min:%x, max:%x, freq:[%d, %d]\n" ,
1557+ "min:%x, max:%x, freq:[%d, %d], thresholds:[%u, %u] \n" ,
15591558 rps -> min_freq , rps -> max_freq ,
15601559 intel_gpu_freq (rps , rps -> min_freq ),
1561- intel_gpu_freq (rps , rps -> max_freq ));
1560+ intel_gpu_freq (rps , rps -> max_freq ),
1561+ rps -> power .up_threshold ,
1562+ rps -> power .down_threshold );
15621563
15631564 GEM_BUG_ON (rps -> max_freq < rps -> min_freq );
15641565 GEM_BUG_ON (rps -> idle_freq > rps -> max_freq );
@@ -2011,6 +2012,10 @@ void intel_rps_init(struct intel_rps *rps)
20112012 }
20122013 }
20132014
2015+ /* Set default thresholds in % */
2016+ rps -> power .up_threshold = 95 ;
2017+ rps -> power .down_threshold = 85 ;
2018+
20142019 /* Finally allow us to boost to max by default */
20152020 rps -> boost_freq = rps -> max_freq ;
20162021 rps -> idle_freq = rps -> min_freq ;
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