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Hansen Dsouzaalexdeucher
Hansen Dsouza
authored and
alexdeucher
committed
drm/amd/display: Fix flickering caused by dccg
Always allow un-gating. Follow legacy workaround for repeated dppclk dto updates Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 29d3d6a commit 9888773

3 files changed

Lines changed: 72 additions & 73 deletions

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‎drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -328,6 +328,17 @@
328328
type DPSTREAMCLK1_GATE_DISABLE;\
329329
type DPSTREAMCLK2_GATE_DISABLE;\
330330
type DPSTREAMCLK3_GATE_DISABLE;\
331+
type SYMCLKA_FE_GATE_DISABLE;\
332+
type SYMCLKB_FE_GATE_DISABLE;\
333+
type SYMCLKC_FE_GATE_DISABLE;\
334+
type SYMCLKD_FE_GATE_DISABLE;\
335+
type SYMCLKE_FE_GATE_DISABLE;\
336+
type SYMCLKA_GATE_DISABLE;\
337+
type SYMCLKB_GATE_DISABLE;\
338+
type SYMCLKC_GATE_DISABLE;\
339+
type SYMCLKD_GATE_DISABLE;\
340+
type SYMCLKE_GATE_DISABLE;\
341+
331342

332343
#define DCCG401_REG_FIELD_LIST(type) \
333344
type OTG0_TMDS_PIXEL_RATE_DIV;\

‎drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c‎

Lines changed: 61 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
2424

2525
#include "reg_helper.h"
2626
#include "core_types.h"
27+
#include "resource.h"
2728
#include "dcn35_dccg.h"
2829

2930
#define TO_DCN_DCCG(dccg)\
@@ -136,7 +137,7 @@ static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool enable)
136137
{
137138
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
138139

139-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
140+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && enable)
140141
return;
141142

142143
switch (inst) {
@@ -165,7 +166,7 @@ static void dccg35_set_symclk32_se_rcg(
165166
{
166167
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
167168

168-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
169+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)
169170
return;
170171

171172
/* SYMCLK32_ROOT_SE#_GATE_DISABLE will clock gate in DCCG */
@@ -204,7 +205,7 @@ static void dccg35_set_symclk32_le_rcg(
204205
{
205206
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
206207

207-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
208+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable)
208209
return;
209210

210211
switch (inst) {
@@ -231,7 +232,7 @@ static void dccg35_set_physymclk_rcg(
231232
{
232233
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
233234

234-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
235+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable)
235236
return;
236237

237238
switch (inst) {
@@ -262,35 +263,45 @@ static void dccg35_set_physymclk_rcg(
262263
}
263264

264265
static void dccg35_set_symclk_fe_rcg(
265-
struct dccg *dccg,
266-
int inst,
267-
bool enable)
266+
struct dccg *dccg,
267+
int inst,
268+
bool enable)
268269
{
269270
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
270271

271-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
272+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)
272273
return;
273274

274275
switch (inst) {
275276
case 0:
277+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
278+
SYMCLKA_FE_GATE_DISABLE, enable ? 0 : 1);
276279
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
277-
SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
280+
SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
278281
break;
279282
case 1:
283+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
284+
SYMCLKB_FE_GATE_DISABLE, enable ? 0 : 1);
280285
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
281-
SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
286+
SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
282287
break;
283288
case 2:
289+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
290+
SYMCLKC_FE_GATE_DISABLE, enable ? 0 : 1);
284291
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
285-
SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
292+
SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
286293
break;
287294
case 3:
295+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
296+
SYMCLKD_FE_GATE_DISABLE, enable ? 0 : 1);
288297
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
289-
SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
298+
SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
290299
break;
291300
case 4:
301+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
302+
SYMCLKE_FE_GATE_DISABLE, enable ? 0 : 1);
292303
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
293-
SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
304+
SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 0 : 1);
294305
break;
295306
default:
296307
BREAK_TO_DEBUGGER();
@@ -307,27 +318,37 @@ static void dccg35_set_symclk_be_rcg(
307318
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
308319

309320
/* TBD add symclk_be in rcg control bits */
310-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)
321+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable)
311322
return;
312323

313324
switch (inst) {
314325
case 0:
326+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
327+
SYMCLKA_GATE_DISABLE, enable ? 0 : 1);
315328
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
316329
SYMCLKA_ROOT_GATE_DISABLE, enable ? 0 : 1);
317330
break;
318331
case 1:
332+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
333+
SYMCLKB_GATE_DISABLE, enable ? 0 : 1);
319334
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
320335
SYMCLKB_ROOT_GATE_DISABLE, enable ? 0 : 1);
321336
break;
322337
case 2:
338+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
339+
SYMCLKC_GATE_DISABLE, enable ? 0 : 1);
323340
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
324341
SYMCLKC_ROOT_GATE_DISABLE, enable ? 0 : 1);
325342
break;
326343
case 3:
344+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
345+
SYMCLKD_GATE_DISABLE, enable ? 0 : 1);
327346
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
328347
SYMCLKD_ROOT_GATE_DISABLE, enable ? 0 : 1);
329348
break;
330349
case 4:
350+
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
351+
SYMCLKE_GATE_DISABLE, enable ? 0 : 1);
331352
REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,
332353
SYMCLKE_ROOT_GATE_DISABLE, enable ? 0 : 1);
333354
break;
@@ -342,7 +363,7 @@ static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable)
342363

343364
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
344365

345-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
366+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)
346367
return;
347368

348369
switch (inst) {
@@ -370,7 +391,7 @@ static void dccg35_set_dppclk_rcg(struct dccg *dccg,
370391

371392
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
372393

373-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
394+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)
374395
return;
375396

376397
switch (inst) {
@@ -399,7 +420,7 @@ static void dccg35_set_dpstreamclk_rcg(
399420
{
400421
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
401422

402-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
423+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable)
403424
return;
404425

405426
switch (inst) {
@@ -436,7 +457,7 @@ static void dccg35_set_smclk32_se_rcg(
436457
{
437458
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
438459

439-
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
460+
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable)
440461
return;
441462

442463
switch (inst) {
@@ -1693,6 +1714,12 @@ static void dccg35_disable_symclk32_se(
16931714
}
16941715
}
16951716

1717+
static void dccg35_init_cb(struct dccg *dccg)
1718+
{
1719+
(void)dccg;
1720+
/* Any RCG should be done when driver enter low power mode*/
1721+
}
1722+
16961723
void dccg35_init(struct dccg *dccg)
16971724
{
16981725
int otg_inst;
@@ -2043,8 +2070,6 @@ static void dccg35_set_dpstreamclk_cb(
20432070
enum dtbclk_source dtb_clk_src;
20442071
enum dp_stream_clk_source dp_stream_clk_src;
20452072

2046-
ASSERT(otg_inst >= DP_STREAM_DTBCLK_P5);
2047-
20482073
switch (src) {
20492074
case REFCLK:
20502075
dtb_clk_src = DTBCLK_REFCLK;
@@ -2099,6 +2124,13 @@ static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst,
20992124
{
21002125
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
21012126

2127+
if (dccg->dpp_clock_gated[dpp_inst]) {
2128+
/*
2129+
* Do not update the DPPCLK DTO if the clock is stopped.
2130+
*/
2131+
return;
2132+
}
2133+
21022134
if (dccg->ref_dppclk && req_dppclk) {
21032135
int ref_dppclk = dccg->ref_dppclk;
21042136
int modulo, phase;
@@ -2126,19 +2158,20 @@ static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst,
21262158
}
21272159

21282160
static void dccg35_dpp_root_clock_control_cb(
2129-
struct dccg *dccg,
2130-
unsigned int dpp_inst,
2131-
bool power_on)
2161+
struct dccg *dccg,
2162+
unsigned int dpp_inst,
2163+
bool power_on)
21322164
{
2165+
if (dccg->dpp_clock_gated[dpp_inst] == power_on)
2166+
return;
21332167
/* power_on set indicates we need to ungate
21342168
* Currently called from optimize_bandwidth and prepare_bandwidth calls
21352169
* Since clock source is not passed restore to refclock on ungate
21362170
* Redundant as gating when enabled is acheived through update_dpp_dto
21372171
*/
2138-
if (power_on)
2139-
dccg35_enable_dpp_clk_new(dccg, dpp_inst, DPP_REFCLK);
2140-
else
2141-
dccg35_disable_dpp_clk_new(dccg, dpp_inst);
2172+
dccg35_set_dppclk_rcg(dccg, dpp_inst, !power_on);
2173+
2174+
dccg->dpp_clock_gated[dpp_inst] = !power_on;
21422175
}
21432176

21442177
static void dccg35_enable_symclk32_se_cb(
@@ -2322,7 +2355,7 @@ static const struct dccg_funcs dccg35_funcs_new = {
23222355
.update_dpp_dto = dccg35_update_dpp_dto_cb,
23232356
.dpp_root_clock_control = dccg35_dpp_root_clock_control_cb,
23242357
.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
2325-
.dccg_init = dccg35_init,
2358+
.dccg_init = dccg35_init_cb,
23262359
.set_dpstreamclk = dccg35_set_dpstreamclk_cb,
23272360
.set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating_cb,
23282361
.enable_symclk32_se = dccg35_enable_symclk32_se_cb,

‎drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c‎

Lines changed: 0 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -147,37 +147,6 @@ void dcn35_init_hw(struct dc *dc)
147147
hws->funcs.bios_golden_init(dc);
148148
}
149149

150-
if (!dc->debug.disable_clock_gate) {
151-
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
152-
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
153-
154-
/* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */
155-
REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,
156-
PHYBSYMCLK_ROOT_GATE_DISABLE, 1,
157-
PHYCSYMCLK_ROOT_GATE_DISABLE, 1,
158-
PHYDSYMCLK_ROOT_GATE_DISABLE, 1,
159-
PHYESYMCLK_ROOT_GATE_DISABLE, 1);
160-
161-
REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL4,
162-
DPIASYMCLK0_GATE_DISABLE, 0,
163-
DPIASYMCLK1_GATE_DISABLE, 0,
164-
DPIASYMCLK2_GATE_DISABLE, 0,
165-
DPIASYMCLK3_GATE_DISABLE, 0);
166-
167-
REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0xFFFFFFFF);
168-
REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,
169-
DTBCLK_P0_GATE_DISABLE, 0,
170-
DTBCLK_P1_GATE_DISABLE, 0,
171-
DTBCLK_P2_GATE_DISABLE, 0,
172-
DTBCLK_P3_GATE_DISABLE, 0);
173-
REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,
174-
DPSTREAMCLK0_GATE_DISABLE, 0,
175-
DPSTREAMCLK1_GATE_DISABLE, 0,
176-
DPSTREAMCLK2_GATE_DISABLE, 0,
177-
DPSTREAMCLK3_GATE_DISABLE, 0);
178-
179-
}
180-
181150
// Initialize the dccg
182151
if (res_pool->dccg->funcs->dccg_init)
183152
res_pool->dccg->funcs->dccg_init(res_pool->dccg);
@@ -305,20 +274,6 @@ void dcn35_init_hw(struct dc *dc)
305274

306275
if (!dc->debug.disable_clock_gate) {
307276
/* enable all DCN clock gating */
308-
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
309-
310-
REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, 0,
311-
SYMCLKB_FE_GATE_DISABLE, 0,
312-
SYMCLKC_FE_GATE_DISABLE, 0,
313-
SYMCLKD_FE_GATE_DISABLE, 0,
314-
SYMCLKE_FE_GATE_DISABLE, 0);
315-
REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, 0);
316-
REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, 0,
317-
SYMCLKB_GATE_DISABLE, 0,
318-
SYMCLKC_GATE_DISABLE, 0,
319-
SYMCLKD_GATE_DISABLE, 0,
320-
SYMCLKE_GATE_DISABLE, 0);
321-
322277
REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
323278
}
324279

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