phy: mediatek: hdmi: mt8195: fix prediv bad upper limit test

granquet · vinodkoul · commit 95bd315f0a5e · 2023-07-12T22:27:02.000+05:30
The pll prediv calculus searchs for the smallest prediv that gets the ns_hdmipll_ck in the range of 5 GHz to 12 GHz. A typo in the upper bound test was testing for 5Ghz to 1Ghz Fixes: 45810d4 ("phy: mediatek: add support for phy-mtk-hdmi-mt8195") Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230529-hdmi_phy_fix-v1-1-bf65f53af533@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -253,7 +253,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw,
 	for (i = 0; i < ARRAY_SIZE(txpredivs); i++) {
 		ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i];
 		if (ns_hdmipll_ck >= 5 * GIGA &&
-		    ns_hdmipll_ck <= 1 * GIGA)
+		    ns_hdmipll_ck <= 12 * GIGA)
 			break;
 	}
 	if (i == (ARRAY_SIZE(txpredivs) - 1) &&

Original file line number	Diff line number	Diff line change
`@@ -253,7 +253,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy hdmi_phy, struct clk_hw hw,`
`253`	`253`	`for (i = 0; i < ARRAY_SIZE(txpredivs); i++) {`
`254`	`254`	`ns_hdmipll_ck = 5 * tmds_clk * txposdiv * txpredivs[i];`
`255`	`255`	`if (ns_hdmipll_ck >= 5 * GIGA &&`
`256`		`- ns_hdmipll_ck <= 1 * GIGA)`
	`256`	`+ ns_hdmipll_ck <= 12 * GIGA)`
`257`	`257`	`break;`
`258`	`258`	`}`
`259`	`259`	`if (i == (ARRAY_SIZE(txpredivs) - 1) &&`