Skip to content

Commit 7ed43d8

Browse files
author
Marc Zyngier
committed
KVM: arm64: Use computed masks as sanitisers for FGT registers
Now that we have computed RES0 bits, use them to sanitise the guest view of FGT registers. Signed-off-by: Marc Zyngier <maz@kernel.org>
1 parent 3164899 commit 7ed43d8

1 file changed

Lines changed: 6 additions & 6 deletions

File tree

arch/arm64/kvm/nested.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,8 +1137,8 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
11371137
res0 |= HFGRTR_EL2_nS2POR_EL1;
11381138
if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, AIE, IMP))
11391139
res0 |= (HFGRTR_EL2_nMAIR2_EL1 | HFGRTR_EL2_nAMAIR2_EL1);
1140-
set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1);
1141-
set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1);
1140+
set_sysreg_masks(kvm, HFGRTR_EL2, res0 | hfgrtr_masks.res0, res1);
1141+
set_sysreg_masks(kvm, HFGWTR_EL2, res0 | hfgwtr_masks.res0, res1);
11421142

11431143
/* HDFG[RW]TR_EL2 */
11441144
res0 = res1 = 0;
@@ -1176,7 +1176,7 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
11761176
HDFGRTR_EL2_nBRBDATA);
11771177
if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P2))
11781178
res0 |= HDFGRTR_EL2_nPMSNEVFR_EL1;
1179-
set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1);
1179+
set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | hdfgrtr_masks.res0, res1);
11801180

11811181
/* Reuse the bits from the read-side and add the write-specific stuff */
11821182
if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMUVer, IMP))
@@ -1185,10 +1185,10 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
11851185
res0 |= HDFGWTR_EL2_TRCOSLAR;
11861186
if (!kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceFilt, IMP))
11871187
res0 |= HDFGWTR_EL2_TRFCR_EL1;
1188-
set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1);
1188+
set_sysreg_masks(kvm, HFGWTR_EL2, res0 | hdfgwtr_masks.res0, res1);
11891189

11901190
/* HFGITR_EL2 */
1191-
res0 = HFGITR_EL2_RES0;
1191+
res0 = hfgitr_masks.res0;
11921192
res1 = HFGITR_EL2_RES1;
11931193
if (!kvm_has_feat(kvm, ID_AA64ISAR1_EL1, DPB, DPB2))
11941194
res0 |= HFGITR_EL2_DCCVADP;
@@ -1222,7 +1222,7 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu)
12221222
set_sysreg_masks(kvm, HFGITR_EL2, res0, res1);
12231223

12241224
/* HAFGRTR_EL2 - not a lot to see here */
1225-
res0 = HAFGRTR_EL2_RES0;
1225+
res0 = hafgrtr_masks.res0;
12261226
res1 = HAFGRTR_EL2_RES1;
12271227
if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, V1P1))
12281228
res0 |= ~(res0 | res1);

0 commit comments

Comments
 (0)