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drm/i915/uncore: add intel_uncore_regs() helper
Add a helper for accessing uncore->regs instead of doing it directly. This will help display code reuse with the xe driver. Cc: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230627095128.208071-1-jani.nikula@intel.com
1 parent cbaf758 commit 72e9abc

7 files changed

Lines changed: 26 additions & 21 deletions

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‎drivers/gpu/drm/i915/display/intel_display_irq.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1149,7 +1149,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
11491149

11501150
u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
11511151
{
1152-
void __iomem * const regs = i915->uncore.regs;
1152+
void __iomem * const regs = intel_uncore_regs(&i915->uncore);
11531153
u32 iir;
11541154

11551155
if (!(master_ctl & GEN11_GU_MISC_IRQ))
@@ -1170,7 +1170,7 @@ void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
11701170

11711171
void gen11_display_irq_handler(struct drm_i915_private *i915)
11721172
{
1173-
void __iomem * const regs = i915->uncore.regs;
1173+
void __iomem * const regs = intel_uncore_regs(&i915->uncore);
11741174
const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
11751175

11761176
disable_rpm_wakeref_asserts(&i915->runtime_pm);

‎drivers/gpu/drm/i915/gt/intel_execlists_submission.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3556,16 +3556,16 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
35563556
lrc_init_wa_ctx(engine);
35573557

35583558
if (HAS_LOGICAL_RING_ELSQ(i915)) {
3559-
execlists->submit_reg = uncore->regs +
3559+
execlists->submit_reg = intel_uncore_regs(uncore) +
35603560
i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
3561-
execlists->ctrl_reg = uncore->regs +
3561+
execlists->ctrl_reg = intel_uncore_regs(uncore) +
35623562
i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
35633563

35643564
engine->fw_domain = intel_uncore_forcewake_for_reg(engine->uncore,
35653565
RING_EXECLIST_CONTROL(engine->mmio_base),
35663566
FW_REG_WRITE);
35673567
} else {
3568-
execlists->submit_reg = uncore->regs +
3568+
execlists->submit_reg = intel_uncore_regs(uncore) +
35693569
i915_mmio_reg_offset(RING_ELSP(base));
35703570
}
35713571

‎drivers/gpu/drm/i915/gt/intel_gt_irq.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ static u32
3131
gen11_gt_engine_identity(struct intel_gt *gt,
3232
const unsigned int bank, const unsigned int bit)
3333
{
34-
void __iomem * const regs = gt->uncore->regs;
34+
void __iomem * const regs = intel_uncore_regs(gt->uncore);
3535
u32 timeout_ts;
3636
u32 ident;
3737

@@ -148,7 +148,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
148148
static void
149149
gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
150150
{
151-
void __iomem * const regs = gt->uncore->regs;
151+
void __iomem * const regs = intel_uncore_regs(gt->uncore);
152152
unsigned long intr_dw;
153153
unsigned int bit;
154154

@@ -183,7 +183,7 @@ void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
183183
bool gen11_gt_reset_one_iir(struct intel_gt *gt,
184184
const unsigned int bank, const unsigned int bit)
185185
{
186-
void __iomem * const regs = gt->uncore->regs;
186+
void __iomem * const regs = intel_uncore_regs(gt->uncore);
187187
u32 dw;
188188

189189
lockdep_assert_held(gt->irq_lock);
@@ -404,7 +404,7 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir)
404404

405405
void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl)
406406
{
407-
void __iomem * const regs = gt->uncore->regs;
407+
void __iomem * const regs = intel_uncore_regs(gt->uncore);
408408
u32 iir;
409409

410410
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {

‎drivers/gpu/drm/i915/gt/intel_sa_media.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
2929
* Standalone media shares the general MMIO space with the primary
3030
* GT. We'll re-use the primary GT's mapping.
3131
*/
32-
uncore->regs = i915->uncore.regs;
32+
uncore->regs = intel_uncore_regs(&i915->uncore);
3333
if (drm_WARN_ON(&i915->drm, uncore->regs == NULL))
3434
return -EIO;
3535

‎drivers/gpu/drm/i915/i915_irq.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -423,7 +423,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
423423
static irqreturn_t ilk_irq_handler(int irq, void *arg)
424424
{
425425
struct drm_i915_private *i915 = arg;
426-
void __iomem * const regs = i915->uncore.regs;
426+
void __iomem * const regs = intel_uncore_regs(&i915->uncore);
427427
u32 de_iir, gt_iir, de_ier, sde_ier = 0;
428428
irqreturn_t ret = IRQ_NONE;
429429

@@ -511,7 +511,7 @@ static inline void gen8_master_intr_enable(void __iomem * const regs)
511511
static irqreturn_t gen8_irq_handler(int irq, void *arg)
512512
{
513513
struct drm_i915_private *dev_priv = arg;
514-
void __iomem * const regs = dev_priv->uncore.regs;
514+
void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore);
515515
u32 master_ctl;
516516

517517
if (!intel_irqs_enabled(dev_priv))
@@ -561,7 +561,7 @@ static inline void gen11_master_intr_enable(void __iomem * const regs)
561561
static irqreturn_t gen11_irq_handler(int irq, void *arg)
562562
{
563563
struct drm_i915_private *i915 = arg;
564-
void __iomem * const regs = i915->uncore.regs;
564+
void __iomem * const regs = intel_uncore_regs(&i915->uncore);
565565
struct intel_gt *gt = to_gt(i915);
566566
u32 master_ctl;
567567
u32 gu_misc_iir;
@@ -619,7 +619,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
619619
{
620620
struct drm_i915_private * const i915 = arg;
621621
struct intel_gt *gt = to_gt(i915);
622-
void __iomem * const regs = gt->uncore->regs;
622+
void __iomem * const regs = intel_uncore_regs(gt->uncore);
623623
u32 master_tile_ctl, master_ctl;
624624
u32 gu_misc_iir;
625625

@@ -711,7 +711,7 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
711711
{
712712
struct intel_uncore *uncore = &dev_priv->uncore;
713713

714-
gen8_master_intr_disable(uncore->regs);
714+
gen8_master_intr_disable(intel_uncore_regs(uncore));
715715

716716
gen8_gt_irq_reset(to_gt(dev_priv));
717717
gen8_display_irq_reset(dev_priv);
@@ -727,7 +727,7 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
727727
struct intel_gt *gt = to_gt(dev_priv);
728728
struct intel_uncore *uncore = gt->uncore;
729729

730-
gen11_master_intr_disable(dev_priv->uncore.regs);
730+
gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
731731

732732
gen11_gt_irq_reset(gt);
733733
gen11_display_irq_reset(dev_priv);
@@ -742,7 +742,7 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv)
742742
struct intel_gt *gt;
743743
unsigned int i;
744744

745-
dg1_master_intr_disable(dev_priv->uncore.regs);
745+
dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
746746

747747
for_each_gt(gt, dev_priv, i)
748748
gen11_gt_irq_reset(gt);
@@ -836,7 +836,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
836836
gen8_gt_irq_postinstall(to_gt(dev_priv));
837837
gen8_de_irq_postinstall(dev_priv);
838838

839-
gen8_master_intr_enable(dev_priv->uncore.regs);
839+
gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
840840
}
841841

842842
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -853,7 +853,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
853853

854854
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
855855

856-
gen11_master_intr_enable(uncore->regs);
856+
gen11_master_intr_enable(intel_uncore_regs(uncore));
857857
intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
858858
}
859859

@@ -880,7 +880,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
880880
GEN11_DISPLAY_IRQ_ENABLE);
881881
}
882882

883-
dg1_master_intr_enable(uncore->regs);
883+
dg1_master_intr_enable(intel_uncore_regs(uncore));
884884
intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
885885
}
886886

‎drivers/gpu/drm/i915/intel_uncore.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -496,6 +496,11 @@ static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
496496
return (reg_val & mask) != expected_val ? -EINVAL : 0;
497497
}
498498

499+
static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore)
500+
{
501+
return uncore->regs;
502+
}
503+
499504
/*
500505
* The raw_reg_{read,write} macros are intended as a micro-optimization for
501506
* interrupt handlers so that the pointer indirection on uncore->regs can

‎drivers/gpu/drm/i915/selftests/intel_uncore.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -210,7 +210,7 @@ static int live_forcewake_ops(void *arg)
210210

211211
for_each_engine(engine, gt, id) {
212212
i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
213-
u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
213+
u32 __iomem *reg = intel_uncore_regs(uncore) + engine->mmio_base + r->offset;
214214
enum forcewake_domains fw_domains;
215215
u32 val;
216216

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