1111#include <linux/init.h>
1212#include <linux/irq.h>
1313#include <linux/irqchip.h>
14- #include <linux/irqchip/irq-davinci-cp-intc.h>
1514#include <linux/irqdomain.h>
1615#include <linux/io.h>
1716#include <linux/of.h>
@@ -154,24 +153,20 @@ static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
154153 .xlate = irq_domain_xlate_onetwocell ,
155154};
156155
157- static int __init
158- davinci_cp_intc_do_init (const struct davinci_cp_intc_config * config ,
159- struct device_node * node )
156+ static int __init davinci_cp_intc_do_init (struct resource * res , unsigned int num_irqs ,
157+ struct device_node * node )
160158{
161- unsigned int num_regs = BITS_TO_LONGS (config -> num_irqs );
159+ unsigned int num_regs = BITS_TO_LONGS (num_irqs );
162160 int offset , irq_base ;
163161 void __iomem * req ;
164162
165- req = request_mem_region (config -> reg .start ,
166- resource_size (& config -> reg ),
167- "davinci-cp-intc" );
163+ req = request_mem_region (res -> start , resource_size (res ), "davinci-cp-intc" );
168164 if (!req ) {
169165 pr_err ("%s: register range busy\n" , __func__ );
170166 return - EBUSY ;
171167 }
172168
173- davinci_cp_intc_base = ioremap (config -> reg .start ,
174- resource_size (& config -> reg ));
169+ davinci_cp_intc_base = ioremap (res -> start , resource_size (res ));
175170 if (!davinci_cp_intc_base ) {
176171 pr_err ("%s: unable to ioremap register range\n" , __func__ );
177172 return - EINVAL ;
@@ -184,37 +179,33 @@ davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
184179
185180 /* Disable system interrupts */
186181 for (offset = 0 ; offset < num_regs ; offset ++ )
187- davinci_cp_intc_write (~0 ,
188- DAVINCI_CP_INTC_SYS_ENABLE_CLR (offset ));
182+ davinci_cp_intc_write (~0 , DAVINCI_CP_INTC_SYS_ENABLE_CLR (offset ));
189183
190184 /* Set to normal mode, no nesting, no priority hold */
191185 davinci_cp_intc_write (0 , DAVINCI_CP_INTC_CTRL );
192186 davinci_cp_intc_write (0 , DAVINCI_CP_INTC_HOST_CTRL );
193187
194188 /* Clear system interrupt status */
195189 for (offset = 0 ; offset < num_regs ; offset ++ )
196- davinci_cp_intc_write (~0 ,
197- DAVINCI_CP_INTC_SYS_STAT_CLR (offset ));
190+ davinci_cp_intc_write (~0 , DAVINCI_CP_INTC_SYS_STAT_CLR (offset ));
198191
199192 /* Enable nIRQ (what about nFIQ?) */
200193 davinci_cp_intc_write (1 , DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET );
201194
195+ /* 4 channels per register */
196+ num_regs = (num_irqs + 3 ) >> 2 ;
202197 /* Default all priorities to channel 7. */
203- num_regs = (config -> num_irqs + 3 ) >> 2 ; /* 4 channels per register */
204198 for (offset = 0 ; offset < num_regs ; offset ++ )
205- davinci_cp_intc_write (0x07070707 ,
206- DAVINCI_CP_INTC_CHAN_MAP (offset ));
199+ davinci_cp_intc_write (0x07070707 , DAVINCI_CP_INTC_CHAN_MAP (offset ));
207200
208- irq_base = irq_alloc_descs (-1 , 0 , config -> num_irqs , 0 );
201+ irq_base = irq_alloc_descs (-1 , 0 , num_irqs , 0 );
209202 if (irq_base < 0 ) {
210- pr_err ("%s: unable to allocate interrupt descriptors: %d\n" ,
211- __func__ , irq_base );
203+ pr_err ("%s: unable to allocate interrupt descriptors: %d\n" , __func__ , irq_base );
212204 return irq_base ;
213205 }
214206
215- davinci_cp_intc_irq_domain = irq_domain_add_legacy (
216- node , config -> num_irqs , irq_base , 0 ,
217- & davinci_cp_intc_irq_domain_ops , NULL );
207+ davinci_cp_intc_irq_domain = irq_domain_add_legacy (node , num_irqs , irq_base , 0 ,
208+ & davinci_cp_intc_irq_domain_ops , NULL );
218209
219210 if (!davinci_cp_intc_irq_domain ) {
220211 pr_err ("%s: unable to create an interrupt domain\n" , __func__ );
@@ -229,31 +220,25 @@ davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
229220 return 0 ;
230221}
231222
232- int __init davinci_cp_intc_init (const struct davinci_cp_intc_config * config )
233- {
234- return davinci_cp_intc_do_init (config , NULL );
235- }
236-
237223static int __init davinci_cp_intc_of_init (struct device_node * node ,
238224 struct device_node * parent )
239225{
240- struct davinci_cp_intc_config config = { };
226+ unsigned int num_irqs ;
227+ struct resource res ;
241228 int ret ;
242229
243- ret = of_address_to_resource (node , 0 , & config . reg );
230+ ret = of_address_to_resource (node , 0 , & res );
244231 if (ret ) {
245- pr_err ("%s: unable to get the register range from device-tree\n" ,
246- __func__ );
232+ pr_err ("%s: unable to get the register range from device-tree\n" , __func__ );
247233 return ret ;
248234 }
249235
250- ret = of_property_read_u32 (node , "ti,intc-size" , & config . num_irqs );
236+ ret = of_property_read_u32 (node , "ti,intc-size" , & num_irqs );
251237 if (ret ) {
252- pr_err ("%s: unable to read the 'ti,intc-size' property\n" ,
253- __func__ );
238+ pr_err ("%s: unable to read the 'ti,intc-size' property\n" , __func__ );
254239 return ret ;
255240 }
256241
257- return davinci_cp_intc_do_init (& config , node );
242+ return davinci_cp_intc_do_init (& res , num_irqs , node );
258243}
259244IRQCHIP_DECLARE (cp_intc , "ti,cp-intc" , davinci_cp_intc_of_init );
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