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accel/amdxdna: Use MSG_OP_CHAIN_EXEC_NPU when supported
MSG_OP_CHAIN_EXEC_NPU is a unified mailbox message that replaces MSG_OP_CHAIN_EXEC_BUFFER_CF and MSG_OP_CHAIN_EXEC_DPU. Add driver logic to check firmware version, and if MSG_OP_CHAIN_EXEC_NPU is supported, uses it to submit firmware commands. Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20251031014700.2919349-1-lizhi.hou@amd.com
1 parent 3668133 commit 71829d7

11 files changed

Lines changed: 392 additions & 167 deletions

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‎drivers/accel/amdxdna/aie2_message.c‎

Lines changed: 286 additions & 157 deletions
Large diffs are not rendered by default.

‎drivers/accel/amdxdna/aie2_msg_priv.h‎

Lines changed: 39 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ enum aie2_msg_opcode {
1919
MSG_OP_CHAIN_EXEC_BUFFER_CF = 0x12,
2020
MSG_OP_CHAIN_EXEC_DPU = 0x13,
2121
MSG_OP_CONFIG_DEBUG_BO = 0x14,
22+
MSG_OP_CHAIN_EXEC_NPU = 0x18,
2223
MSG_OP_MAX_XRT_OPCODE,
2324
MSG_OP_SUSPEND = 0x101,
2425
MSG_OP_RESUME = 0x102,
@@ -149,6 +150,16 @@ struct exec_dpu_req {
149150
__u32 payload[35];
150151
} __packed;
151152

153+
enum exec_npu_type {
154+
EXEC_NPU_TYPE_NON_ELF = 0x1,
155+
EXEC_NPU_TYPE_PARTIAL_ELF = 0x2,
156+
};
157+
158+
union exec_req {
159+
struct execute_buffer_req ebuf;
160+
struct exec_dpu_req dpu_req;
161+
};
162+
152163
struct execute_buffer_resp {
153164
enum aie2_msg_status status;
154165
} __packed;
@@ -320,9 +331,6 @@ struct async_event_msg_resp {
320331
} __packed;
321332

322333
#define MAX_CHAIN_CMDBUF_SIZE SZ_4K
323-
#define slot_has_space(slot, offset, payload_size) \
324-
(MAX_CHAIN_CMDBUF_SIZE >= (offset) + (payload_size) + \
325-
sizeof(typeof(slot)))
326334

327335
struct cmd_chain_slot_execbuf_cf {
328336
__u32 cu_idx;
@@ -340,12 +348,40 @@ struct cmd_chain_slot_dpu {
340348
__u32 args[] __counted_by(arg_cnt);
341349
};
342350

351+
#define MAX_NPU_ARGS_SIZE (26 * sizeof(__u32))
352+
struct cmd_chain_slot_npu {
353+
enum exec_npu_type type;
354+
u64 inst_buf_addr;
355+
u64 save_buf_addr;
356+
u64 restore_buf_addr;
357+
u32 inst_size;
358+
u32 save_size;
359+
u32 restore_size;
360+
u32 inst_prop_cnt;
361+
u32 cu_idx;
362+
u32 arg_cnt;
363+
u32 args[] __counted_by(arg_cnt);
364+
} __packed;
365+
343366
struct cmd_chain_req {
344367
__u64 buf_addr;
345368
__u32 buf_size;
346369
__u32 count;
347370
} __packed;
348371

372+
struct cmd_chain_npu_req {
373+
u32 flags;
374+
u32 reserved;
375+
u64 buf_addr;
376+
u32 buf_size;
377+
u32 count;
378+
} __packed;
379+
380+
union exec_chain_req {
381+
struct cmd_chain_npu_req npu_req;
382+
struct cmd_chain_req req;
383+
};
384+
349385
struct cmd_chain_resp {
350386
enum aie2_msg_status status;
351387
__u32 fail_cmd_idx;

‎drivers/accel/amdxdna/aie2_pci.c‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ struct mgmt_mbox_chann_info {
5555

5656
static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 fw_minor)
5757
{
58+
const struct aie2_fw_feature_tbl *feature;
5859
struct amdxdna_dev *xdna = ndev->xdna;
5960

6061
/*
@@ -78,6 +79,17 @@ static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 f
7879
XDNA_ERR(xdna, "Firmware minor version smaller than supported");
7980
return -EINVAL;
8081
}
82+
83+
for (feature = ndev->priv->fw_feature_tbl; feature && feature->min_minor;
84+
feature++) {
85+
if (fw_minor < feature->min_minor)
86+
continue;
87+
if (feature->max_minor > 0 && fw_minor > feature->max_minor)
88+
continue;
89+
90+
set_bit(feature->feature, &ndev->feature_mask);
91+
}
92+
8193
return 0;
8294
}
8395

@@ -587,6 +599,7 @@ static int aie2_init(struct amdxdna_dev *xdna)
587599
}
588600

589601
release_firmware(fw);
602+
aie2_msg_init(ndev);
590603
amdxdna_pm_init(xdna);
591604
return 0;
592605

‎drivers/accel/amdxdna/aie2_pci.h‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,17 @@ enum aie2_dev_status {
156156
AIE2_DEV_START,
157157
};
158158

159+
struct aie2_exec_msg_ops {
160+
int (*init_cu_req)(struct amdxdna_gem_obj *cmd_bo, void *req,
161+
size_t *size, u32 *msg_op);
162+
int (*init_dpu_req)(struct amdxdna_gem_obj *cmd_bo, void *req,
163+
size_t *size, u32 *msg_op);
164+
void (*init_chain_req)(void *req, u64 slot_addr, size_t size, u32 cmd_cnt);
165+
int (*fill_cf_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
166+
int (*fill_dpu_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
167+
u32 (*get_chain_msg_op)(u32 cmd_op);
168+
};
169+
159170
struct amdxdna_dev_hdl {
160171
struct amdxdna_dev *xdna;
161172
const struct amdxdna_dev_priv *priv;
@@ -173,6 +184,8 @@ struct amdxdna_dev_hdl {
173184
u32 total_col;
174185
struct aie_version version;
175186
struct aie_metadata metadata;
187+
unsigned long feature_mask;
188+
struct aie2_exec_msg_ops *exec_msg_ops;
176189

177190
/* power management and clock*/
178191
enum amdxdna_power_mode_type pw_mode;
@@ -206,12 +219,26 @@ struct aie2_hw_ops {
206219
int (*set_dpm)(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
207220
};
208221

222+
enum aie2_fw_feature {
223+
AIE2_NPU_COMMAND,
224+
AIE2_FEATURE_MAX
225+
};
226+
227+
struct aie2_fw_feature_tbl {
228+
enum aie2_fw_feature feature;
229+
u32 max_minor;
230+
u32 min_minor;
231+
};
232+
233+
#define AIE2_FEATURE_ON(ndev, feature) test_bit(feature, &(ndev)->feature_mask)
234+
209235
struct amdxdna_dev_priv {
210236
const char *fw_path;
211237
u64 protocol_major;
212238
u64 protocol_minor;
213239
const struct rt_config *rt_config;
214240
const struct dpm_clk_freq *dpm_clk_tbl;
241+
const struct aie2_fw_feature_tbl *fw_feature_tbl;
215242

216243
#define COL_ALIGN_NONE 0
217244
#define COL_ALIGN_NATURE 1
@@ -236,6 +263,7 @@ extern const struct dpm_clk_freq npu1_dpm_clk_table[];
236263
extern const struct dpm_clk_freq npu4_dpm_clk_table[];
237264
extern const struct rt_config npu1_default_rt_cfg[];
238265
extern const struct rt_config npu4_default_rt_cfg[];
266+
extern const struct aie2_fw_feature_tbl npu4_fw_feature_table[];
239267

240268
/* aie2_smu.c */
241269
int aie2_smu_init(struct amdxdna_dev_hdl *ndev);
@@ -260,6 +288,7 @@ int aie2_get_array_async_error(struct amdxdna_dev_hdl *ndev,
260288
struct amdxdna_drm_get_array *args);
261289

262290
/* aie2_message.c */
291+
void aie2_msg_init(struct amdxdna_dev_hdl *ndev);
263292
int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev);
264293
int aie2_resume_fw(struct amdxdna_dev_hdl *ndev);
265294
int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value);

‎drivers/accel/amdxdna/amdxdna_ctx.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -113,14 +113,14 @@ void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size)
113113
return &cmd->data[num_masks];
114114
}
115115

116-
int amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
116+
u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
117117
{
118118
struct amdxdna_cmd *cmd = abo->mem.kva;
119119
u32 num_masks, i;
120120
u32 *cu_mask;
121121

122122
if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN)
123-
return -1;
123+
return INVALID_CU_IDX;
124124

125125
num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header);
126126
cu_mask = cmd->data;
@@ -129,7 +129,7 @@ int amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
129129
return ffs(cu_mask[i]) - 1;
130130
}
131131

132-
return -1;
132+
return INVALID_CU_IDX;
133133
}
134134

135135
/*

‎drivers/accel/amdxdna/amdxdna_ctx.h‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,10 @@
1313
struct amdxdna_hwctx_priv;
1414

1515
enum ert_cmd_opcode {
16-
ERT_START_CU = 0,
17-
ERT_CMD_CHAIN = 19,
18-
ERT_START_NPU = 20,
16+
ERT_START_CU = 0,
17+
ERT_CMD_CHAIN = 19,
18+
ERT_START_NPU = 20,
19+
ERT_INVALID_CMD = ~0U,
1920
};
2021

2122
enum ert_cmd_state {
@@ -64,6 +65,8 @@ struct amdxdna_cmd {
6465
u32 data[];
6566
};
6667

68+
#define INVALID_CU_IDX (~0U)
69+
6770
struct amdxdna_hwctx {
6871
struct amdxdna_client *client;
6972
struct amdxdna_hwctx_priv *priv;
@@ -150,7 +153,7 @@ amdxdna_cmd_get_state(struct amdxdna_gem_obj *abo)
150153
}
151154

152155
void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size);
153-
int amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo);
156+
u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo);
154157

155158
void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job);
156159
void amdxdna_hwctx_remove_all(struct amdxdna_client *client);

‎drivers/accel/amdxdna/npu1_regs.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,12 +63,18 @@ const struct dpm_clk_freq npu1_dpm_clk_table[] = {
6363
{ 0 }
6464
};
6565

66+
static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = {
67+
{ .feature = AIE2_NPU_COMMAND, .min_minor = 8 },
68+
{ 0 }
69+
};
70+
6671
static const struct amdxdna_dev_priv npu1_dev_priv = {
6772
.fw_path = "amdnpu/1502_00/npu.sbin",
6873
.protocol_major = 0x5,
6974
.protocol_minor = 0x7,
7075
.rt_config = npu1_default_rt_cfg,
7176
.dpm_clk_tbl = npu1_dpm_clk_table,
77+
.fw_feature_tbl = npu1_fw_feature_table,
7278
.col_align = COL_ALIGN_NONE,
7379
.mbox_dev_addr = NPU1_MBOX_BAR_BASE,
7480
.mbox_size = 0, /* Use BAR size */

‎drivers/accel/amdxdna/npu2_regs.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ static const struct amdxdna_dev_priv npu2_dev_priv = {
6767
.protocol_minor = 0x6,
6868
.rt_config = npu4_default_rt_cfg,
6969
.dpm_clk_tbl = npu4_dpm_clk_table,
70+
.fw_feature_tbl = npu4_fw_feature_table,
7071
.col_align = COL_ALIGN_NATURE,
7172
.mbox_dev_addr = NPU2_MBOX_BAR_BASE,
7273
.mbox_size = 0, /* Use BAR size */

‎drivers/accel/amdxdna/npu4_regs.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,12 +83,18 @@ const struct dpm_clk_freq npu4_dpm_clk_table[] = {
8383
{ 0 }
8484
};
8585

86+
const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = {
87+
{ .feature = AIE2_NPU_COMMAND, .min_minor = 15 },
88+
{ 0 }
89+
};
90+
8691
static const struct amdxdna_dev_priv npu4_dev_priv = {
8792
.fw_path = "amdnpu/17f0_10/npu.sbin",
8893
.protocol_major = 0x6,
8994
.protocol_minor = 12,
9095
.rt_config = npu4_default_rt_cfg,
9196
.dpm_clk_tbl = npu4_dpm_clk_table,
97+
.fw_feature_tbl = npu4_fw_feature_table,
9298
.col_align = COL_ALIGN_NATURE,
9399
.mbox_dev_addr = NPU4_MBOX_BAR_BASE,
94100
.mbox_size = 0, /* Use BAR size */

‎drivers/accel/amdxdna/npu5_regs.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ static const struct amdxdna_dev_priv npu5_dev_priv = {
6767
.protocol_minor = 12,
6868
.rt_config = npu4_default_rt_cfg,
6969
.dpm_clk_tbl = npu4_dpm_clk_table,
70+
.fw_feature_tbl = npu4_fw_feature_table,
7071
.col_align = COL_ALIGN_NATURE,
7172
.mbox_dev_addr = NPU5_MBOX_BAR_BASE,
7273
.mbox_size = 0, /* Use BAR size */

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