Skip to content

Commit 62af738

Browse files
airliedairlied
committed
Merge tag 'amd-drm-fixes-6.6-2023-10-04' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.6-2023-10-04: amdgpu: - Add missing unique_id for GC 11.0.3 - Fix memory leak in FRU error path - Fix PCIe link reporting on some SMU 11 parts - Fix ACPI _PR3 detection - Fix DISPCLK WDIVIDER handling in OTG code Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231005034358.7824-1-alexander.deucher@amd.com
2 parents dd01714 + b206011 commit 62af738

6 files changed

Lines changed: 30 additions & 23 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2093,7 +2093,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
20932093
adev->flags |= AMD_IS_PX;
20942094

20952095
if (!(adev->flags & AMD_IS_APU)) {
2096-
parent = pci_upstream_bridge(adev->pdev);
2096+
parent = pcie_find_root_port(adev->pdev);
20972097
adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
20982098
}
20992099

‎drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -170,6 +170,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
170170
csum += pia[size - 1];
171171
if (csum) {
172172
DRM_ERROR("Bad Product Info Area checksum: 0x%02x", csum);
173+
kfree(pia);
173174
return -EIO;
174175
}
175176

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct
157157
int32_t N;
158158
int32_t j;
159159

160-
if (!pipe_ctx->stream)
160+
if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
161161
continue;
162162
/* Virtual encoders don't have this function */
163163
if (!stream_enc->funcs->get_fifo_cal_average_level)
@@ -188,7 +188,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct
188188
int32_t N;
189189
int32_t j;
190190

191-
if (!pipe_ctx->stream)
191+
if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
192192
continue;
193193
/* Virtual encoders don't have this function */
194194
if (!stream_enc->funcs->get_fifo_cal_average_level)

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -355,7 +355,7 @@ static void dcn32_update_clocks_update_dentist(
355355
int32_t N;
356356
int32_t j;
357357

358-
if (!pipe_ctx->stream)
358+
if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
359359
continue;
360360
/* Virtual encoders don't have this function */
361361
if (!stream_enc->funcs->get_fifo_cal_average_level)
@@ -401,7 +401,7 @@ static void dcn32_update_clocks_update_dentist(
401401
int32_t N;
402402
int32_t j;
403403

404-
if (!pipe_ctx->stream)
404+
if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
405405
continue;
406406
/* Virtual encoders don't have this function */
407407
if (!stream_enc->funcs->get_fifo_cal_average_level)

‎drivers/gpu/drm/amd/pm/amdgpu_pm.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2040,6 +2040,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
20402040
case IP_VERSION(11, 0, 0):
20412041
case IP_VERSION(11, 0, 1):
20422042
case IP_VERSION(11, 0, 2):
2043+
case IP_VERSION(11, 0, 3):
20432044
*states = ATTR_STATE_SUPPORTED;
20442045
break;
20452046
default:

‎drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c‎

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2082,36 +2082,41 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
20822082
return ret;
20832083
}
20842084

2085+
#define MAX(a, b) ((a) > (b) ? (a) : (b))
2086+
20852087
static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
20862088
uint32_t pcie_gen_cap,
20872089
uint32_t pcie_width_cap)
20882090
{
20892091
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
20902092
struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2091-
u32 smu_pcie_arg;
2093+
uint8_t *table_member1, *table_member2;
2094+
uint32_t min_gen_speed, max_gen_speed;
2095+
uint32_t min_lane_width, max_lane_width;
2096+
uint32_t smu_pcie_arg;
20922097
int ret, i;
20932098

2094-
/* PCIE gen speed and lane width override */
2095-
if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2096-
if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap)
2097-
pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1];
2099+
GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2100+
GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
20982101

2099-
if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap)
2100-
pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1];
2102+
min_gen_speed = MAX(0, table_member1[0]);
2103+
max_gen_speed = MIN(pcie_gen_cap, table_member1[1]);
2104+
min_gen_speed = min_gen_speed > max_gen_speed ?
2105+
max_gen_speed : min_gen_speed;
2106+
min_lane_width = MAX(1, table_member2[0]);
2107+
max_lane_width = MIN(pcie_width_cap, table_member2[1]);
2108+
min_lane_width = min_lane_width > max_lane_width ?
2109+
max_lane_width : min_lane_width;
21012110

2102-
/* Force all levels to use the same settings */
2103-
for (i = 0; i < NUM_LINK_LEVELS; i++) {
2104-
pcie_table->pcie_gen[i] = pcie_gen_cap;
2105-
pcie_table->pcie_lane[i] = pcie_width_cap;
2106-
}
2111+
if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2112+
pcie_table->pcie_gen[0] = max_gen_speed;
2113+
pcie_table->pcie_lane[0] = max_lane_width;
21072114
} else {
2108-
for (i = 0; i < NUM_LINK_LEVELS; i++) {
2109-
if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2110-
pcie_table->pcie_gen[i] = pcie_gen_cap;
2111-
if (pcie_table->pcie_lane[i] > pcie_width_cap)
2112-
pcie_table->pcie_lane[i] = pcie_width_cap;
2113-
}
2115+
pcie_table->pcie_gen[0] = min_gen_speed;
2116+
pcie_table->pcie_lane[0] = min_lane_width;
21142117
}
2118+
pcie_table->pcie_gen[1] = max_gen_speed;
2119+
pcie_table->pcie_lane[1] = max_lane_width;
21152120

21162121
for (i = 0; i < NUM_LINK_LEVELS; i++) {
21172122
smu_pcie_arg = (i << 16 |

0 commit comments

Comments
 (0)