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surajk8aknautiyal
surajk8
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aknautiyal
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drm/i915/dsc: Add rc_range_parameter calculation for YCbCr420
Some rc_range_parameter calculations were missed for YCbCr420, add them to calculate_rc_param() --v2 -take into account the new formula to get bpp_i --v4 -Fix range_bpg_offset formula for YCbCr420 bpp <= 16 [Ankit] --v5 -Fix comment and mention use of DSC C Model [Ankit] Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230710162456.2736949-1-suraj.kandpal@intel.com
1 parent 9550099 commit 580c7e3

1 file changed

Lines changed: 103 additions & 38 deletions

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‎drivers/gpu/drm/i915/display/intel_vdsc.c‎

Lines changed: 103 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -52,23 +52,33 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
5252
return true;
5353
}
5454

55+
static void
56+
intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
57+
int bpp)
58+
{
59+
int bpc = vdsc_cfg->bits_per_component;
60+
61+
/* Read range_minqp and range_max_qp from qp tables */
62+
vdsc_cfg->rc_range_params[buf].range_min_qp =
63+
intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420);
64+
vdsc_cfg->rc_range_params[buf].range_max_qp =
65+
intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
66+
}
67+
68+
/*
69+
* We are using the method provided in DSC 1.2a C-Model in codec_main.c
70+
* Above method use a common formula to derive values for any combination of DSC
71+
* variables. The formula approach may yield slight differences in the derived PPS
72+
* parameters from the original parameter sets. These differences are not consequential
73+
* to the coding performance because all parameter sets have been shown to produce
74+
* visually lossless quality (provides the same PPS values as
75+
* DSCParameterValuesVESA V1-2 spreadsheet).
76+
*/
5577
static void
5678
calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
5779
{
5880
int bpc = vdsc_cfg->bits_per_component;
5981
int bpp = vdsc_cfg->bits_per_pixel >> 4;
60-
static const s8 ofs_und6[] = {
61-
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
62-
};
63-
static const s8 ofs_und8[] = {
64-
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
65-
};
66-
static const s8 ofs_und12[] = {
67-
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
68-
};
69-
static const s8 ofs_und15[] = {
70-
10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
71-
};
7282
int qp_bpc_modifier = (bpc - 8) * 2;
7383
u32 res, buf_i, bpp_i;
7484

@@ -119,33 +129,88 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
119129
vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
120130
vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
121131

122-
bpp_i = (2 * (bpp - 6));
123-
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
124-
u8 range_bpg_offset;
125-
126-
/* Read range_minqp and range_max_qp from qp tables */
127-
vdsc_cfg->rc_range_params[buf_i].range_min_qp =
128-
intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
129-
vdsc_cfg->rc_range_params[buf_i].range_max_qp =
130-
intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
131-
132-
/* Calculate range_bpg_offset */
133-
if (bpp <= 6) {
134-
range_bpg_offset = ofs_und6[buf_i];
135-
} else if (bpp <= 8) {
136-
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
137-
range_bpg_offset = ofs_und6[buf_i] + res;
138-
} else if (bpp <= 12) {
139-
range_bpg_offset = ofs_und8[buf_i];
140-
} else if (bpp <= 15) {
141-
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
142-
range_bpg_offset = ofs_und12[buf_i] + res;
143-
} else {
144-
range_bpg_offset = ofs_und15[buf_i];
132+
if (vdsc_cfg->native_420) {
133+
static const s8 ofs_und4[] = {
134+
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
135+
};
136+
static const s8 ofs_und5[] = {
137+
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
138+
};
139+
static const s8 ofs_und6[] = {
140+
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
141+
};
142+
static const s8 ofs_und8[] = {
143+
10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
144+
};
145+
146+
bpp_i = bpp - 8;
147+
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
148+
u8 range_bpg_offset;
149+
150+
intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
151+
152+
/* Calculate range_bpg_offset */
153+
if (bpp <= 8) {
154+
range_bpg_offset = ofs_und4[buf_i];
155+
} else if (bpp <= 10) {
156+
res = DIV_ROUND_UP(((bpp - 8) *
157+
(ofs_und5[buf_i] - ofs_und4[buf_i])), 2);
158+
range_bpg_offset = ofs_und4[buf_i] + res;
159+
} else if (bpp <= 12) {
160+
res = DIV_ROUND_UP(((bpp - 10) *
161+
(ofs_und6[buf_i] - ofs_und5[buf_i])), 2);
162+
range_bpg_offset = ofs_und5[buf_i] + res;
163+
} else if (bpp <= 16) {
164+
res = DIV_ROUND_UP(((bpp - 12) *
165+
(ofs_und8[buf_i] - ofs_und6[buf_i])), 4);
166+
range_bpg_offset = ofs_und6[buf_i] + res;
167+
} else {
168+
range_bpg_offset = ofs_und8[buf_i];
169+
}
170+
171+
vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
172+
range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
173+
}
174+
} else {
175+
static const s8 ofs_und6[] = {
176+
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
177+
};
178+
static const s8 ofs_und8[] = {
179+
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
180+
};
181+
static const s8 ofs_und12[] = {
182+
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
183+
};
184+
static const s8 ofs_und15[] = {
185+
10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
186+
};
187+
188+
bpp_i = (2 * (bpp - 6));
189+
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
190+
u8 range_bpg_offset;
191+
192+
intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
193+
194+
/* Calculate range_bpg_offset */
195+
if (bpp <= 6) {
196+
range_bpg_offset = ofs_und6[buf_i];
197+
} else if (bpp <= 8) {
198+
res = DIV_ROUND_UP(((bpp - 6) *
199+
(ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
200+
range_bpg_offset = ofs_und6[buf_i] + res;
201+
} else if (bpp <= 12) {
202+
range_bpg_offset = ofs_und8[buf_i];
203+
} else if (bpp <= 15) {
204+
res = DIV_ROUND_UP(((bpp - 12) *
205+
(ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
206+
range_bpg_offset = ofs_und12[buf_i] + res;
207+
} else {
208+
range_bpg_offset = ofs_und15[buf_i];
209+
}
210+
211+
vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
212+
range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
145213
}
146-
147-
vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
148-
range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
149214
}
150215
}
151216

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