drm/msm: Fix range size vs end confusion

robclark · robclark · commit 537fef808be5 · 2022-04-11T09:36:13.000-07:00
The fourth param is size, rather than range_end. Note that we could increase the address space size if we had a way to prevent buffers from spanning a 4G split, mostly just to avoid fw bugs with 64b math. Fixes: 84c31ee ("drm/msm/a6xx: Add support for per-instance pagetables") Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220407202836.1211268-1-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu)
 		return ERR_CAST(mmu);
 
 	return msm_gem_address_space_create(mmu,
-		"gpu", 0x100000000ULL, 0x1ffffffffULL);
+		"gpu", 0x100000000ULL, SZ_4G);
 }
 
 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)

Original file line number	Diff line number	Diff line change
`@@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu)`
`1742`	`1742`	`return ERR_CAST(mmu);`
`1743`	`1743`
`1744`	`1744`	`return msm_gem_address_space_create(mmu,`
`1745`		`- "gpu", 0x100000000ULL, 0x1ffffffffULL);`
	`1745`	`+ "gpu", 0x100000000ULL, SZ_4G);`
`1746`	`1746`	`}`
`1747`	`1747`
`1748`	`1748`	`static uint32_t a6xx_get_rptr(struct msm_gpu gpu, struct msm_ringbuffer ring)`