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tmlind
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clocksource/drivers/timer-ti-dm: Move inline functions to driver for am6
The __omap_dm_timer_* inline functions in the header are no longer needed outside the driver, and the header ifdefs prevent the driver working for ARCH_K3. Let's move the inline functions to the driver and drop the ifdefs and drop the unused functions __omap_dm_timer_override_errata() and __omap_dm_timer_load_start(). Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220408101715.43697-2-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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2 files changed

Lines changed: 115 additions & 144 deletions

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‎drivers/clocksource/timer-ti-dm.c‎

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,121 @@ enum {
4444
REQUEST_BY_NODE,
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};
4646

47+
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
48+
int posted)
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{
50+
if (posted)
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while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
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cpu_relax();
53+
54+
return readl_relaxed(timer->func_base + (reg & 0xff));
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}
56+
57+
static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
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u32 reg, u32 val, int posted)
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{
60+
if (posted)
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while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
62+
cpu_relax();
63+
64+
writel_relaxed(val, timer->func_base + (reg & 0xff));
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}
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67+
static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
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{
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u32 tidr;
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/* Assume v1 ip if bits [31:16] are zero */
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tidr = readl_relaxed(timer->io_base);
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if (!(tidr >> 16)) {
74+
timer->revision = 1;
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timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
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timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
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timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
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timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
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timer->func_base = timer->io_base;
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} else {
81+
timer->revision = 2;
82+
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
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timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
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timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
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timer->pend = timer->io_base +
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_OMAP_TIMER_WRITE_PEND_OFFSET +
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OMAP_TIMER_V2_FUNC_OFFSET;
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timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
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}
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}
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/*
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* __omap_dm_timer_enable_posted - enables write posted mode
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* @timer: pointer to timer instance handle
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*
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* Enables the write posted mode for the timer. When posted mode is enabled
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* writes to certain timer registers are immediately acknowledged by the
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* internal bus and hence prevents stalling the CPU waiting for the write to
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* complete. Enabling this feature can improve performance for writing to the
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* timer registers.
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*/
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static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
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{
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if (timer->posted)
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return;
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if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
108+
timer->posted = OMAP_TIMER_NONPOSTED;
109+
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
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return;
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}
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__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
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OMAP_TIMER_CTRL_POSTED, 0);
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timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
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timer->posted = OMAP_TIMER_POSTED;
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}
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static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
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int posted, unsigned long rate)
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{
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u32 l;
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l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
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if (l & OMAP_TIMER_CTRL_ST) {
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l &= ~0x1;
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__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
128+
#ifdef CONFIG_ARCH_OMAP2PLUS
129+
/* Readback to make sure write has completed */
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__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
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/*
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* Wait for functional clock period x 3.5 to make sure that
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* timer is stopped
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*/
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udelay(3500000 / rate + 1);
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#endif
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}
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/* Ack possibly pending interrupt */
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writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
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}
142+
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static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
144+
unsigned int value)
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{
146+
writel_relaxed(value, timer->irq_ena);
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__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
148+
}
149+
150+
static inline unsigned int
151+
__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
152+
{
153+
return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
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}
155+
156+
static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
157+
unsigned int value)
158+
{
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writel_relaxed(value, timer->irq_stat);
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}
161+
47162
/**
48163
* omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
49164
* @timer: timer pointer over which read operation to perform

‎include/clocksource/timer-ti-dm.h‎

Lines changed: 0 additions & 144 deletions
Original file line numberDiff line numberDiff line change
@@ -247,148 +247,4 @@ int omap_dm_timers_active(void);
247247
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
248248
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
249249

250-
/*
251-
* The below are inlined to optimize code size for system timers. Other code
252-
* should not need these at all.
253-
*/
254-
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2PLUS)
255-
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
256-
int posted)
257-
{
258-
if (posted)
259-
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
260-
cpu_relax();
261-
262-
return readl_relaxed(timer->func_base + (reg & 0xff));
263-
}
264-
265-
static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
266-
u32 reg, u32 val, int posted)
267-
{
268-
if (posted)
269-
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
270-
cpu_relax();
271-
272-
writel_relaxed(val, timer->func_base + (reg & 0xff));
273-
}
274-
275-
static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
276-
{
277-
u32 tidr;
278-
279-
/* Assume v1 ip if bits [31:16] are zero */
280-
tidr = readl_relaxed(timer->io_base);
281-
if (!(tidr >> 16)) {
282-
timer->revision = 1;
283-
timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
284-
timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
285-
timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
286-
timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
287-
timer->func_base = timer->io_base;
288-
} else {
289-
timer->revision = 2;
290-
timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
291-
timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
292-
timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
293-
timer->pend = timer->io_base +
294-
_OMAP_TIMER_WRITE_PEND_OFFSET +
295-
OMAP_TIMER_V2_FUNC_OFFSET;
296-
timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
297-
}
298-
}
299-
300-
/*
301-
* __omap_dm_timer_enable_posted - enables write posted mode
302-
* @timer: pointer to timer instance handle
303-
*
304-
* Enables the write posted mode for the timer. When posted mode is enabled
305-
* writes to certain timer registers are immediately acknowledged by the
306-
* internal bus and hence prevents stalling the CPU waiting for the write to
307-
* complete. Enabling this feature can improve performance for writing to the
308-
* timer registers.
309-
*/
310-
static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
311-
{
312-
if (timer->posted)
313-
return;
314-
315-
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
316-
timer->posted = OMAP_TIMER_NONPOSTED;
317-
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
318-
return;
319-
}
320-
321-
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
322-
OMAP_TIMER_CTRL_POSTED, 0);
323-
timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
324-
timer->posted = OMAP_TIMER_POSTED;
325-
}
326-
327-
/**
328-
* __omap_dm_timer_override_errata - override errata flags for a timer
329-
* @timer: pointer to timer handle
330-
* @errata: errata flags to be ignored
331-
*
332-
* For a given timer, override a timer errata by clearing the flags
333-
* specified by the errata argument. A specific erratum should only be
334-
* overridden for a timer if the timer is used in such a way the erratum
335-
* has no impact.
336-
*/
337-
static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
338-
u32 errata)
339-
{
340-
timer->errata &= ~errata;
341-
}
342-
343-
static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
344-
int posted, unsigned long rate)
345-
{
346-
u32 l;
347-
348-
l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
349-
if (l & OMAP_TIMER_CTRL_ST) {
350-
l &= ~0x1;
351-
__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
352-
#ifdef CONFIG_ARCH_OMAP2PLUS
353-
/* Readback to make sure write has completed */
354-
__omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
355-
/*
356-
* Wait for functional clock period x 3.5 to make sure that
357-
* timer is stopped
358-
*/
359-
udelay(3500000 / rate + 1);
360-
#endif
361-
}
362-
363-
/* Ack possibly pending interrupt */
364-
writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
365-
}
366-
367-
static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
368-
u32 ctrl, unsigned int load,
369-
int posted)
370-
{
371-
__omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
372-
__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
373-
}
374-
375-
static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
376-
unsigned int value)
377-
{
378-
writel_relaxed(value, timer->irq_ena);
379-
__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
380-
}
381-
382-
static inline unsigned int
383-
__omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
384-
{
385-
return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
386-
}
387-
388-
static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
389-
unsigned int value)
390-
{
391-
writel_relaxed(value, timer->irq_stat);
392-
}
393-
#endif /* CONFIG_ARCH_OMAP1 || CONFIG_ARCH_OMAP2PLUS */
394250
#endif /* __CLOCKSOURCE_DMTIMER_H */

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