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Ulf Hansson
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pmdomain: Merge branch dt into next
Merge the immutable branch dt into next, to allow the DT bindings to be tested together with changes that are targeted for v6.19. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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‎Documentation/devicetree/bindings/power/mediatek,mt8196-gpufreq.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/mediatek,mt8196-gpufreq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MFlexGraphics Power and Frequency Controller
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maintainers:
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- Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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description:
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A special-purpose embedded MCU to control power and frequency of GPU devices
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using MediaTek Flexible Graphics integration hardware.
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properties:
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$nodename:
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pattern: '^power-controller@[a-f0-9]+$'
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compatible:
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enum:
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- mediatek,mt8196-gpufreq
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reg:
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items:
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- description: GPR memory area
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- description: RPC memory area
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- description: SoC variant ID register
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reg-names:
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items:
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- const: gpr
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- const: rpc
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- const: hw-revision
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clocks:
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items:
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- description: main clock of the embedded controller (EB)
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- description: core PLL
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- description: stack 0 PLL
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- description: stack 1 PLL
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clock-names:
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items:
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- const: eb
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- const: core
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- const: stack0
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- const: stack1
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mboxes:
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items:
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- description: FastDVFS events
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- description: frequency control
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- description: sleep control
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- description: timer control
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- description: frequency hopping control
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- description: hardware voter control
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- description: FastDVFS control
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mbox-names:
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items:
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- const: fast-dvfs-event
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- const: gpufreq
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- const: sleep
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- const: timer
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- const: fhctl
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- const: ccf
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- const: fast-dvfs
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memory-region:
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items:
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- description: phandle to the GPUEB shared memory
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"#clock-cells":
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const: 1
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"#power-domain-cells":
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const: 0
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- mboxes
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- mbox-names
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- memory-region
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- "#clock-cells"
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- "#power-domain-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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power-controller@4b09fd00 {
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compatible = "mediatek,mt8196-gpufreq";
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reg = <0x4b09fd00 0x80>,
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<0x4b800000 0x1000>,
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<0x4b860128 0x4>;
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reg-names = "gpr", "rpc", "hw-revision";
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clocks = <&topckgen CLK_TOP_MFG_EB>,
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<&mfgpll CLK_MFG_AO_MFGPLL>,
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<&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>,
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<&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>;
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clock-names = "eb", "core", "stack0", "stack1";
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mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>,
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<&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>,
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<&gpueb_mbox 7>;
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mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl",
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"ccf", "fast-dvfs";
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memory-region = <&gpueb_shared_memory>;
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#clock-cells = <1>;
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#power-domain-cells = <0>;
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};

‎Documentation/devicetree/bindings/power/mediatek,power-controller.yaml‎

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- mediatek,mt8188-power-controller
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- mediatek,mt8192-power-controller
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- mediatek,mt8195-power-controller
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- mediatek,mt8196-hwv-hfrp-power-controller
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- mediatek,mt8196-hwv-scp-power-controller
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- mediatek,mt8196-power-controller
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- mediatek,mt8365-power-controller
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'#power-domain-cells':
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contains:
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enum:
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- mediatek,mt8183-power-controller
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- mediatek,mt8196-power-controller
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then:
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properties:
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access-controllers:

‎Documentation/devicetree/bindings/power/qcom,rpmpd.yaml‎

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oneOf:
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- enum:
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- qcom,glymur-rpmhpd
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- qcom,kaanapali-rpmhpd
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- qcom,mdm9607-rpmpd
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- qcom,milos-rpmhpd
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- qcom,msm8226-rpmpd

‎Documentation/devicetree/bindings/power/rockchip,power-controller.yaml‎

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- rockchip,rk3576-power-controller
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- rockchip,rk3588-power-controller
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- rockchip,rv1126-power-controller
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- rockchip,rv1126b-power-controller
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"#power-domain-cells":
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const: 1
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"include/dt-bindings/power/rk3568-power.h"
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"include/dt-bindings/power/rk3588-power.h"
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"include/dt-bindings/power/rockchip,rv1126-power.h"
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"include/dt-bindings/power/rockchip,rv1126b-power-controller.h"
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clocks:
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minItems: 1

‎Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml‎

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maintainers:
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- Nicolas Saenz Julienne <nsaenz@kernel.org>
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allOf:
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- $ref: /schemas/watchdog/watchdog.yaml#
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properties:
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compatible:
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items:
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- enum:
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- brcm,bcm2835-pm
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- brcm,bcm2711-pm
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- brcm,bcm2712-pm
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- const: brcm,bcm2835-pm-wdt
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reg:
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minItems: 2
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minItems: 1
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maxItems: 3
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reg-names:
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minItems: 2
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minItems: 1
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items:
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- const: pm
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- const: asb
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- reg
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- "#power-domain-cells"
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- "#reset-cells"
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- clocks
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allOf:
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- $ref: /schemas/watchdog/watchdog.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- brcm,bcm2835-pm
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- brcm,bcm2711-pm
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then:
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required:
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- clocks
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properties:
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reg:
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minItems: 2
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reg-names:
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minItems: 2
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else:
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properties:
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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additionalProperties: false
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‎include/dt-bindings/power/mediatek,mt8196-power.h‎

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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2025 Collabora Ltd
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef _DT_BINDINGS_POWER_MT8196_POWER_H
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#define _DT_BINDINGS_POWER_MT8196_POWER_H
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/* SCPSYS Secure Power Manager - Direct Control */
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#define MT8196_POWER_DOMAIN_MD 0
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#define MT8196_POWER_DOMAIN_CONN 1
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#define MT8196_POWER_DOMAIN_SSUSB_P0 2
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#define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0 3
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#define MT8196_POWER_DOMAIN_SSUSB_P1 4
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#define MT8196_POWER_DOMAIN_SSUSB_P23 5
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#define MT8196_POWER_DOMAIN_SSUSB_PHY_P2 6
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#define MT8196_POWER_DOMAIN_PEXTP_MAC0 7
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#define MT8196_POWER_DOMAIN_PEXTP_MAC1 8
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#define MT8196_POWER_DOMAIN_PEXTP_MAC2 9
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#define MT8196_POWER_DOMAIN_PEXTP_PHY0 10
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#define MT8196_POWER_DOMAIN_PEXTP_PHY1 11
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#define MT8196_POWER_DOMAIN_PEXTP_PHY2 12
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#define MT8196_POWER_DOMAIN_AUDIO 13
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#define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT 14
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#define MT8196_POWER_DOMAIN_ADSP_INFRA 15
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#define MT8196_POWER_DOMAIN_ADSP_AO 16
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/* SCPSYS Secure Power Manager - HW Voter */
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#define MT8196_POWER_DOMAIN_MM_PROC_DORMANT 0
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#define MT8196_POWER_DOMAIN_SSR 1
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/* HFRPSYS MultiMedia Power Control (MMPC) - HW Voter */
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#define MT8196_POWER_DOMAIN_VDE0 0
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#define MT8196_POWER_DOMAIN_VDE1 1
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#define MT8196_POWER_DOMAIN_VDE_VCORE0 2
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#define MT8196_POWER_DOMAIN_VEN0 3
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#define MT8196_POWER_DOMAIN_VEN1 4
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#define MT8196_POWER_DOMAIN_VEN2 5
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#define MT8196_POWER_DOMAIN_DISP_VCORE 6
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#define MT8196_POWER_DOMAIN_DIS0_DORMANT 7
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#define MT8196_POWER_DOMAIN_DIS1_DORMANT 8
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#define MT8196_POWER_DOMAIN_OVL0_DORMANT 9
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#define MT8196_POWER_DOMAIN_OVL1_DORMANT 10
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#define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT 11
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#define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT 12
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#define MT8196_POWER_DOMAIN_MML0_SHUTDOWN 13
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#define MT8196_POWER_DOMAIN_MML1_SHUTDOWN 14
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#define MT8196_POWER_DOMAIN_MM_INFRA0 15
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#define MT8196_POWER_DOMAIN_MM_INFRA1 16
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#define MT8196_POWER_DOMAIN_MM_INFRA_AO 17
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#define MT8196_POWER_DOMAIN_CSI_BS_RX 18
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#define MT8196_POWER_DOMAIN_CSI_LS_RX 19
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#define MT8196_POWER_DOMAIN_DSI_PHY0 20
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#define MT8196_POWER_DOMAIN_DSI_PHY1 21
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#define MT8196_POWER_DOMAIN_DSI_PHY2 22
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#endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */

‎include/dt-bindings/power/qcom,rpmhpd.h‎

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#define RPMH_REGULATOR_LEVEL_RETENTION 16
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#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3 50
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1 51
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1 54
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60
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#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_L0 76
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80
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#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96
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#define RPMH_REGULATOR_LEVEL_SVS 128

‎include/dt-bindings/power/rockchip,rv1126b-power-controller.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
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#define __DT_BINDINGS_POWER_RV1126B_POWER_CONTROLLER_H__
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/* VD_NPU */
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#define RV1126B_PD_NPU 0
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/* VD_LOGIC */
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#define RV1126B_PD_VDO 1
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#define RV1126B_PD_AIISP 2
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#endif

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